Novel low loss dual-trench superjunction IGBT with semi-floating P-pillar

Abstract

—In this paper, a novel dual-trench superjunction insulated gate bipolar transistor with semi-floating P-pillar (DTSFP-SJ-IGBT) is proposed and studied by simulation. The P-pillar of DTSFP-SJ-IGBT is semi-floating because only a portion is located below the trench gate, while a small part remains directly connected to the P-base. This small part P-pillar is depleted by the gate voltage in the on-state to enhance the carrier-storage effect, and provides an extraction hole path in the turning-off state to reduce the loss. The dual-trench structure results in a more uniform electric field distribution within the device while enhancing the carrier storage effect in the pillar regions. The simulation results show that at the same on-state voltage (VCE(sat)) of 1.30 V, the turn-off loss (Eoff) of the DTSFP-SJ-IGBT is 38.46 % lower than that of the superjunction IGBT with floating P-pillar (FP-SJ-IGBT), and 27.93 % lower than that of the recently reported superjunction IGBT with self-adaptive hole-extraction path (SAHE-SJ-IGBT). At the same Eoff of 1.00 mJ/cm2, the VCE(sat) of the DTSFP-SJ-IGBT is 44.70 % lower than that of the conventional superjunction IGBT (Con-SJ-IGBT).