Successive Approximation Register Analog-to-digital Converter Research Articles

A Review on Fundamentals of Noise-Shaping SAR ADCs and Design Considerations

A general overview of Noise-Shaping Successive Approximation Register (SAR) analog-to-digital converters is provided, encompassing the fundamentals, operational principles, and key architectures of Noise-Shaping SAR (NS SAR). Key challenges, including inherent errors in processing circuits, are examined, along with current advancements in architecture design. Various issues, such as loop filter optimization, implementation methods, and DAC network element mismatches, are explored, along with considerations for voltage converter performance. The design of dynamic comparators is examined, highlighting their critical role in the SAR ADC architecture. Various architectures of dynamic comparators are extensively explored, including optimization techniques, performance considerations, and emerging trends. Finally, emerging trends and future challenges in the field are discussed.

An Energy-Efficient 12-Bit VCO-Based Incremental Zoom ADC with Fast Phase-Alignment Scheme for Multi-Channel Biomedical Applications

This paper presents a low-power, energy-efficient, 12-bit incremental zoom analog-to-digital converter (ADC) for multi-channel bio-signal acquisitions. The ADC consists of a 7-stage ring voltage-controlled oscillator (VCO)-based incremental ΔΣ modulator (I-ΔΣM) and an 8-bit successive approximation register (SAR) ADC. The proposed VCO-based I-ΔΣM can provide fast phase-alignment of the ring-VCO to reduce the interval settling time; thereby, the I-ΔΣM can accommodate time-division-multiplexed input signals without phase leakage between consecutive measurements. The SAR ADC also adopts splitting unit capacitors that can support VCM-free tri-level switching and prevent invalid states from the phase frequency detector with minimal logic gates and switches. The proposed ADC has been fabricated in a standard 180 nm standard 1P6M CMOS process, exhibiting a 67-dB peak signal-to-noise ratio, a 74-dB dynamic range, and a Walden figure of merit of 19.12 fJ/c-s, while consuming a power of 3.51 μW with a sampling rate of 100 kS/s.

Energy‐efficient switching method using input‐swapping for high‐resolution successive approximation register analog‐to‐digital converters

AbstractThis paper presents an energy‐efficient digital‐to‐analog converter (DAC) switching method with low common‐mode variations for high‐resolution successive approximation register (SAR) analog‐to‐digital converters (ADCs), while enabling to implement resolutions such as 14‐bit as compared to the typical 10‐bit. The proposed switching method enables high resolution by having a nearly constant common‐mode voltage and employing input‐swapping to use the reference voltage (Vref) only in the sampling phase. This method eliminates the need for the third reference voltage during the entire DAC switching steps, which reduces the required number of switches at the bottom plates of the capacitors. The use of lower number of switches not only lowers the DAC control logic complexity, but also results in a faster operation, lower power, and smaller area. When compared to conventional 10‐bit SAR ADCs, the proposed switching method in a 10‐bit implementation reduces the average energy and area by 96.09% and 75%, respectively, while offering high‐resolution implementation options such as 14 bits.

Flexible and fully integrated 4-bit SAR ADC using metal-oxide TFTs

This paper presents a flexible fully integrated 4-bit successive approximation register (SAR) analog-to-digital converter (ADC), which is fabricated by unipolar n-type indium-zinc-oxide thin-film transistors. A bootstrap switch and a comparator with a pre-amplifier are proposed and employed to realize the SAR ADC. The fabricated SAR ADC achieves a sampling rate of up to 20 kHz and a peak signal-to-noise and distortion ratio of 22.9 dB, corresponding to an effective-number-of-bits of 3.52 bits. The static performance of −0.58/+0.37 LSB DNL and −0.49/+0.39 LSB INL is achieved.

A bridged‐switch energy‐efficient switching scheme for SAR ADCs with 2× input range

AbstractIn recent years, successive approximation register (SAR) analogue‐to‐digital converters (ADCs) have been widely applied in Internet of Things (IoT) sensor devices. To reduce the power consumption of ADCs, a bridged‐switch energy‐efficient switching scheme for SAR ADCs with a 2× input range is proposed. Due to the use of top‐plate sampling, overall shift and bridged switch, the energy consumption of the first three comparisons and reset is zero, meanwhile the energy consumption of the fifth comparison is greatly reduced. The proposed switching scheme has an average energy consumption of 13.084CVref2, which reduces the switching energy by 99.04% compared to the conventional switching scheme. The proposed switching scheme can achieve a 2× input range with the same supply voltage, effectively reducing ADC power consumption and making it more suitable for IoT applications.

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

In this study, a high-performance 16-bit, 500 MS/s successive approximation register analog-to-digital con-verter (SAR-ADC) with variable body biasing (VBB) for re-ducing sub-threshold leakage is designed and optimized. The suggested ADC architecture makes use of a voltage threshold complementary metal-oxide-semiconductor (VTCMOS) cir-cuit with Widlar current mirror technology to efficiently con-sume 39.2 μW at an operating voltage of 1.0 V. Notably, the optimized ADC achieves outstanding performance measures, such as a signal-to-noise and distortion ratio (SNDR) of 97 dB and a total harmonic distortion (THD) of -97.97 dB, which are crucial markers of the ADC's accuracy and fidelity. An over-view of the growing need for high-resolution ADCs in contem-porary high-speed data conversion systems opens the study. The main goal of this effort is to improve overall ADC per-formance and tackle the problem of sub-threshold leakage. The Widlar current mirror technology and the VTCMOS cir-cuit are integrated for enhanced linearity, decreased current mismatch errors, and minimized leakage current. This inte-gration is highlighted in the full explanation of the ADC de-sign. The advent of the VBB approach as a successful method of leakage reduction is a significant contribution to this re-search. The theoretical foundations and workings of the VBB technique are discussed, and thorough simulations and tests are used to assess how the VBB technique affects leakage cur-rent and circuit performance. The SAR-ADC design and simulations were carried out using Cadence Virtuoso soft-ware.

Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications

This study gives a thorough analysis of the performance of a 45 nm CMOS process-designed 16-bit 500 MS/s successive approximation register analog-to-digital converter (SAR-ADC). 16-bit R-2R DAC double-tail dynamic latch, Widlar current method, variable body-biasing technique, sample and hold block, 16-bit SAR, and 16-bit latch are used to design proposed SAR-ADC block. The SAR-ADC design and simulations were carried out using Cadence Virtuoso software. This powerful electronic design automation (EDA) tool facilitated the design, layout, and simulation of the ADC, ensuring a comprehensive analysis of its performance characteristics. MATLAB was used for post-simulation data analysis, processing, and visualization. The proposed SAR-ADC is compared with few existing examples listed as ADS8881, LTC2380–16, ADS8344, LTC2368, and MAX11156 on the performance metrics including signal-to-noise ratio (SNR), figure of merit (FOM), total harmonic distortion (THD), resolution, delay, power consumption and figure of Merit (FOM). This work is highlighting different aspects of the suggested architecture and demonstrates how it outperforms benchmark of ADCs in terms of power usage, SNR, THD, and FOM. A SAR-ADC attains a power consumption of 39.2 μW while operating at sampling frequency of 500 MS s–1 at supply voltage of 1 V. The results provide fresh perspectives for potential improvements in existing work in terms of reduction in power consumption and high-speed ADC at 16-bit resolution and also Jitter is scrutinized across various stages of the SAR-ADC. The proposed low power, high speed and high-resolution SAR ADC is targeted for high-quality analog-to-digital signal conversion useful in industrial automation systems, medical devices, IoT and audio processing modules.

A High ENOB 14-Bit ADC without Calibration

This paper presents an implementation of a 14-bit 2.5 MS/s differential Successive-Approximation-Register (SAR) analog-to-digital converter (ADC) to be used for sensing multiple analog input signals. A differential binary-weighted with split capacitance charge-redistribution capacitive digital-to-analog converter (CDAC) utilizing the conventional switching technique is designed, without using any calibration mechanism for fast power-on operation. The CDAC capacitor unit has been optimized for improved linearity without calibration technique. The SAR ADC has a differential input range 3.6 Vpp, with a SNDR of 80.45 dB, ENOB of 13.07, SFDR of 87.16 dB and dissipates an average power of 0.8 mW, while operating at 2.5 V/1 V for analog/digital power supply. The INL and DNL is +0.22/−0.34 LSB and +0.42/−0.3 LSB, respectively. A prototype ADC has been fabricated in a conventional CMOS 65 nm technology process.

Radiation Detector Front-End Readout Chip with Nonbinary Successive Approximation Register Analog-to-Digital Converter for Wearable Healthcare Monitoring Applications.

A 16-channel front-end readout chip for a radiation detector is designed for portable or wearable healthcare monitoring applications. The proposed chip reads the signal of the radiation detector and converts it into digital serial-out data by using a nonbinary successive approximation register (SAR) analog-to-digital converter (ADC) that has a 1-MS/s sampling rate and 10-b resolution. The minimum-to-maximum differential and integral nonlinearity are measured as -0.32 to 0.33 and -0.43 to 0.37 least significant bits, respectively. The signal-to-noise-and-distortion ratio and effective number of bits are 57.41 dB and 9.24 bits, respectively, for an input frequency of 500 kHz and a sampling rate of 1 MS/s. The SAR ADC has a 38.9-fJ/conversion step figure of merit at the sampling rate of 1 MS/s. The proposed chip can read input signals with peak currents ranging from 20 to 750 μA and convert the analog signal into a 10-bit serial-output digital signal. The input dynamic range is 2-75 pC. The resolution of the peak current is 208.3 nA. The chip, which has an area of 1.444 mm × 10.568 mm, is implemented using CMOS 0.18-μm 1P6M technology, and the power consumption of each channel is 19 mW. This design is suitable for wearable devices, especially biomedical devices.

A 78 dB 0.417 mW Second-Order NS SAR ADC with Dynamic Amplifier-Assisted Integrator

The noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is an innovative hybrid structure that offers performance advantages. The NS-SAR ADC leverages the SAR ADC as its foundation and combines oversampling technology and noise-shaping technology found in Sigma-Delta ADC. This integration effectively combines the strengths of both structures and enhances overall performance. The ADC features a simple circuit structure, compact chip area, and high energy efficiency, which has positioned it as a prominent research area. In this paper, leveraging the TSMC 65 nm GP process, the NS-SAR ADC is designed with a power supply voltage of 1 V. This design adopts an 8-bit differential capacitor structure, operates at a sampling frequency of 16 MS/s, and achieves an oversampling rate of 16 times the desired performance indicators. Through extensive circuit post simulation verification, the SNR obtained reaches 78 dB, providing an effective bit resolution of 12.7 bits. The core chip area of the ADC measures 366 × 333 μm2, while the power consumption is impressively low at 417 μW and FoMs is 168 dB.

A Wireless Multimodal Physiological Monitoring ASIC for Animal Health Monitoring Injectable Devices.

Utilizing injectable devices for monitoring animal health offers several advantages over traditional wearable devices, including improved signal-to-noise ratio (SNR) and enhanced immunity to motion artifacts. We present a wireless application-specific integrated circuit (ASIC) for injectable devices. The ASIC has multiple physiological sensing modalities including body temperature monitoring, electrocardiography (ECG), and photoplethysmography (PPG). The ASIC fabricated using the CMOS 180 nm process is sized to fit into an injectable microchip implant. The ASIC features a low-power design, drawing an average DC power of 155.3 μW, enabling the ASIC to be wirelessly powered through an inductive link. To capture the ECG signal, we designed the ECG analog frontend (AFE) with 0.3 Hz low cut-off frequency and 45-79 dB adjustable midband gain. To measure PPG, we employ an energy-efficient and safe switched-capacitor-based (SC) light emitting diode (LED) driver to illuminate an LED with milliampere-level current pulses. A SC integrator-based AFE converts the current of photodiode with a programmable transimpedance gain. A resistor-based Wheatstone Bridge (WhB) temperature sensor followed by an instrumentation amplifier (IA) provides 27-47 °C sensing range with 0.02 °C inaccuracy. Recorded physiological signals are sequentially sampled and quantized by a 10-bit analog-to-digital converter (ADC) with the successive approximation register (SAR) architecture. The SAR ADC features an energy-efficient switching scheme and achieves a 57.5 dB signal-to-noise-and-distortion ratio (SNDR) within 1 kHz bandwidth. Then, a back data telemetry transmits the baseband data via a backscatter scheme with intermediate-frequency assistance. The ASIC's overall functionality and performance has been evaluated through an in vivo experiment.

Ultra-low power 10-bit 50–90 MSps SAR ADCs in 65 nm CMOS for multi-channel ASICs

The design and measurement results of ultra-low power, fast 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) prototypes in 65 nm CMOS technology are presented. Eight prototype ADCs were designed using two different switching schemes of capacitive Digital-to-Analog Converter (DAC), based on MIM or MOM capacitors, and controlled by standard or low-power SAR logic. The layout of each ADC prototype is drawn in 60 μm pitch to make it ready for multi-channel implementation. A series of measurements have been made confirming that all prototypes are fully functional, and six of them achieve very good quantitative performance. Five out of eight ADCs show both integral (INL) and differential (DNL) nonlinearity errors below 1 LSB. In dynamic measurements performed at 0.1 Nyquist input frequency, the effective number of bits (ENOB) between 8.9–9.3 was obtained for different ADC prototypes. Standard ADC versions work up to 80–90 MSps with ENOB between 8.9–9.2 bits at the highest sampling rate, while the low-power versions work up to above 50 MSps with ENOB around 9.3 bits at 40 MSps. The power consumption is linear with the sample rate and at 40 MSps it is around 400 μW for the low-power ADCs and just over 500 μW for the standard ADCs. At 80 MSps the standard ADCs consume about 1 mW.

Design of Low Power SAR ADC with Novel Regenerative Comparator

This paper introduces two low-power design techniques for a successive approximation register (SAR) analog-to-digital converter (ADC) used in transmitting physiological signals. The first technique is called dual split switching, involving the use of a one-sided charge-scaling digital-to-analog converter (DAC) to minimize switching energy by reducing leakage in a dual transmission gate. The second technique, known as the set and reset phase, determines the amplification and comparison phases of the comparator. This approach reduces the delay time of the comparator through the use of a folded cascode pre-amplifier and a regenerative latch. The design includes a Serial-in-Parallel-Out (SIPO) N-bit register and SAR, implemented using negative edge-triggered D flip-flops (DFFs). To optimize power consumption, the supply voltage of the SAR ADC is set to 500 mV. The concept of a variable threshold is utilized throughout the design to enable operation with this lower supply voltage. The SAR ADC is designed to support a sampling rate of up to 1 Msps (mega-samples per second). The circuit is implemented using standard UMC180nm technology. According to the test results, the power consumption of the SAR ADC is only 29.06 uW, and the achieved sampling rate is 5 Ksps (kilo-samples per second). The maximum differential non-linearity (DNL) is measured to be +0.9/−0.82 least significant bits (LSBs).

A Bridged-Switch Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converters with a Low-Complexity Capacitor Drive Circuit

In recent years, due to the rise of the Internet of Things (IoT), various sensors have come to be in great demand for IoT devices. Analog-to-digital converters (ADCs) act as an important part of receivers in sensors. To improve the uptime of IoT devices, a bridged-switch energy-efficient switching scheme for successive approximation register (SAR) ADCs with a low-complexity capacitor drive circuit is proposed. The technique of top-plate sampling and closed-loop charge recycling is used in the proposed switching scheme so that neither the first nor the second comparison consumes switching energy. The third comparison uses bridge switches to connect the subarray to the main array, effectively reducing switching’s energy consumption. Only the least significant bit (LSB) is dependent on the accuracy of Vcm; thus, the last comparison consumes little switching energy. The proposed switching scheme achieves an average switching energy value of 47.5 CV2ref, which is 96.52% lower than that of the conventional capacitor switching scheme and reduces the area by 75%. The other major circuit modules employed are bootstrapped switches, a fully dynamic comparator, and dynamic SAR logic. The proposed ADC was simulated under the conditions of 180 nm CMOS process and 1 MS/s, resulting in a 9.8-bit effective number of bits (ENOB), a signal-to-noise and distortion ratio (SNDR) of 60.76 dB, a spurious-free dynamic range (SFDR) of 69.85 dB, a power consumption of 14.7 μW, and a figure of merit (FoM) of 16.55 fJ/conv.-step.

Design of a 0.4 V, 8.43 ENOB, 5.29 nW, 2 kS/s SAR ADC for Implantable Devices

This paper presents a 9-bit differential, minimum-powered, successive approximation register (SAR) ADC intended for implantable devices or sensors. Such applications demand nanowatt-range power consumption, which is achieved by designing the SAR ADC with a proposed bootstrap switch, bespoke split-capacitive DAC, customized comparator and a modified dynamic bit-slice unit for SAR logic. The linearity of the ADC is improved by introducing a bootstrap switch with a low clock feedthrough and threshold voltage variations along with the disseminated attenuation capacitor in the split-capacitive DAC. The dynamic comparator is customized to be simple in terms of the number of transistors to gain the advantage of low power and is also designed to have a low dynamic offset voltage. The stacking concept is embedded in the bit-slice unit of SAR logic to achieve reduced leakage power. This paper is concerned with how to contribute to low power consumption in all the aspects possible related to the implementation of the SAR ADC. With a 0.4 V supply and at 2 kS/s, the proposed ADC achieves an SNDR of 52.52 dB and a power consumption of 5.29 nW, resulting in a figure of merit (FOM) of 7.66 fJ/conversion-step.

A 10-bit 160 MS/s Asynchronous SAR ADC design

This study describes a 10-bit 160 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) design in a 40 nm CMOS technical process. The SAR ADC is provided with an improved capacitive digital-to-analog converter (CDAC), and the capacitor array is featured by six split high-bit capacitors and a combination of splitting and monotonic switching schemes. This structure and switching scheme can both save power and improve speed while introducing negligible common-mode voltage change. An improved double-tail comparator and TSPC D flip-flops are implemented to further enhance the speed. Simulation results show that the ADC achieves SFDR 72.17 dB, SNDR 61.37 dB, and ENOB 9.90 bits at Nyquist input frequency. The power consumption of the ADC under a 1.2 V power supply is 2.808 mW, achieving 18.4 fJ/conv FoM.

Power-Aware Quantization in Analog In-Memory Computing With STT-MRAM Macro

Analog in-memory computing (AiMC) reduces the cost of data transfer by processing data inside memory. Compared with other emerging nonvolatile memories, AiMC with magnetic random-access memory (MRAM) shows potential with logic compatible supply voltage, small variability issues, and high endurance. However, the analog output of the array must be converted to digital using an analog-to-digital converter (ADC), which significantly offsets the benefits of AiMC. This paper presents power-aware quantization circuits in AiMC with spin transfer torque MRAM (STT-MRAM) macro, in which a successive approximation register (SAR) ADC with reconfigurable 3/4-bit resolution and 250MS/s sampling rate addresses the need of high speed and low power for AiMC. By using 28-nm CMOS process, simulation results show that the proposed ADC consumes only 31.6 μW at a 900mV supply and 250MS/s. 10.4-25.7 TOPS/W is realized with 2-bit input, 1-bit weight, and 4-bit output convolution neural network (CNN).

Multi-detector simultaneous sampling design in the spot-scanning defects detection system

With the decreases in semiconductor critical dimension and increases in circuit intricacy, the impact of wafer defects on the yield and manufacturing cost of integrated circuits is becoming increasingly significant. In this paper, a multimodal spot-scanning defect detection system designed for unpatterned wafer surfaces is introduced. The defect detection system's mechanics, electronics, and software are introduced, focusing on presenting a multi-detector simultaneous sampling design. The signal sampling is based on the position triggering of the rotary stage encoder. The focused illumination spot is scanned in a helical trajectory relative to the wafer in coordination with the motion of the linear stage and rotary stage. The signal detection is carried out synchronously, and the signal sampling is triggered by rotary stage encoder position pulses to achieve equally spaced sampling. The detector signals are trans-impedance amplified and transmitted differentially to transfer the analogue signals from the optical head to the main control board. Under FPGA control, the main control board completes the simultaneous sampling and signal processing through nine high-precision 16-bit SAR(successive-approximation-register) ADCs(analogue-to-digital converter) under the trigger signal. The defect detection system is designed with a pixel resolution of 4 × 4 μm, requiring a sampling position error of less than 1 pixel and an inter-channel position deviation of less than 0.1 pixel. The rotary stage prototype has a design speed of 120 rpm, and the positioning accuracy of the encoder is ±8 arcsec. Therefore, the maximum sampling position error is 1.94 μm for a 4-inch wafer sample. The maximum phase deviation between the nine channels is 32.5 ns, and the maximum position deviation is 20.4 nm.

Design of 8 -bit low power SAR ADC in 45 nm for biomedical implants

The utilisation of low power SAR (Successive Approximation Register) Analog-to-Digital Converters holds significant importance in the domain of bio-medical signal acquisition. The present study showcases the utilisation of an 8-bit CMOS SAR-ADC for integration into the analog front end of bio-signal acquisition. The focus of this technology pertains to the monitoring of implanted bio-signal devices, with a specific emphasis on ECG/EEG signals. A capacitive digital-to-analog converter (DAC) is suggested as a means to attain power consumption in the microwatt range. This approach enables comparisons to be made without any energy consumption, leading to a substantial enhancement in energy efficiency. Furthermore, a comprehensive theoretical examination of comparator offset voltages has been conducted to enhance the offset performance of the comparator operating at low supply voltage. The analysis indicates that optimization of the comparator is achieved solely through the adjustment of transistor sizes, without the implementation of any specific offset cancellation techniques. Simulations indicate that the optimization of the offset voltage to approximately 5 mV occurs when there is variation in the common-mode input voltage at a 1 V supply. The proposed Analog-to-Digital Converter (ADC) layout has been successfully executed utilizing the 45 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The Analog-to-Digital Converter (ADC) attains a Spurious-Free Dynamic Range (SFDR) of 64.02 dB and consumes 1.9 μW of power at a sampling rate of 1.1 MHz and a supply voltage of 1 V.

A 14-bit 1-MS/s SAR ADC with a segmented capacitor array and background mismatch calibration for IoT sensing applications

A 14-bit 1-MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) for IoT sensing devices is proposed. With a VCM-based switching scheme, the 14-bit SAR ADC can lower 68.7 % switching energy consumption and 97.9 % capacitor array area by utilizing a segmented capacitor array compared to the conventional binary capacitor array. Although the root-mean-square integral nonlinearity (INL) and differential nonlinearity (DNL) of the segmented capacitor array is decreased compared with the binary capacitor array at the capacitance mismatch of 1 %, the capacitor mismatch can be background calibrated and the power consumption of the digital calibration circuit is increased by only 55.4 μW under the identical calibration step condition, and there is no noticeable deterioration in the calibration speed, resulting in a significant improvement in power efficiency. In addition, a voltage-controlled oscillator (VCO)-based comparator based on the reset-in-time technique and the adaptive stage adjustment technique is employed to further reduce power consumption. Post-simulation results show that the proposed 14-bit prototype SAR ADC can enhance the signal-to-noise distortion ratio (SNDR) and spurious-free dynamic range (SFDR) by 13.35 dB and 16.72 dB respectively at a Nyquist input rate and a sampling rate of 1-MS/s. With a power supply of 1.8 V, the power consumption is 597.8 μW with a figure of merit (FoM) value of 83.3 fJ/Conv.-step in a 0.18-μm CMOS process. The total area is 0.208 mm2, of which the analog part is only 0.038 mm2.