Energy‐efficient switching method using input‐swapping for high‐resolution successive approximation register analog‐to‐digital converters

Abstract

AbstractThis paper presents an energy‐efficient digital‐to‐analog converter (DAC) switching method with low common‐mode variations for high‐resolution successive approximation register (SAR) analog‐to‐digital converters (ADCs), while enabling to implement resolutions such as 14‐bit as compared to the typical 10‐bit. The proposed switching method enables high resolution by having a nearly constant common‐mode voltage and employing input‐swapping to use the reference voltage (Vref) only in the sampling phase. This method eliminates the need for the third reference voltage during the entire DAC switching steps, which reduces the required number of switches at the bottom plates of the capacitors. The use of lower number of switches not only lowers the DAC control logic complexity, but also results in a faster operation, lower power, and smaller area. When compared to conventional 10‐bit SAR ADCs, the proposed switching method in a 10‐bit implementation reduces the average energy and area by 96.09% and 75%, respectively, while offering high‐resolution implementation options such as 14 bits.