Subthreshold Current Research Articles

Dynamical response of Autaptic Izhikevich Neuron disturbed by Gaussian white noise.

Using the improved memristive Izhikevich neuron model, the effects of autaptic connection as well as electromagnetic induction are studied on the dynamical behavior of neuronal spiking. Using bifurcation analysis for membrane potentials, the effects of autaptic and electromagnetic parameters on the mode transition in electrical activities of the neuron model are investigated. Furthermore, white Gaussian noise is considered in the neuron model, to evaluate the effect of electromagnetic disturbance on the firing pattern of the neuron using the coefficient of variation. The bifurcation diagram versus autaptic conductance and time delay has been extensively studied. The results show that the effects of autaptic connection as well as electromagnetic induction on the spiking behavior of neurons can be well demonstrated by using the Izhikevich model. The electrical activities of the Izhikevich neuron model become more complex when the effects of autaptic connection and electromagnetic induction are considered in the neuron model. Using the Izhikevich neuron model, the high variety of spiking/bursting patterns is represented in the bifurcation diagram of inter-spike interval versus autaptic or electromagnetic parameters. Noise can have distinct effects on the spiking activity of the neuron, for the subthreshold input current, increasing the intensity of the electromagnetic noise increases the regularity of the neuron spiking, but for the suprathreshold input current, the regularity of spiking decreases with noise.

Analysis of performance for novel pocket-doped NCFET under the influence of interface trap charges and temperature variation

This paper explores the DC characteristics and trap analysis of single gate NCFET (SG-NCFET) and highly doped double pocket double gate NCFET (HDDP-DG-NCFET) with spacer at different temperatures. The effect of temperature and the trap charges (Uniform and Gaussian) on various electrical parameters is investigated to determine the device's reliability. In addition, this work investigates the effect of interface (Si–SiO2) traps on the operation of NCFET, a potential developing technology that intends to achieve a steep sub-threshold slope. The presence of traps at interface degrades threshold voltage and sub-threshold swing. Hence, the work investigates the effect of various concentrations of trap at the oxide-semiconductor boundary on the sub-threshold swing, ON current, threshold voltage, OFF current, and current switching ratio of both the devices (SG-NCFET and HDDP-DG-NCFET). In this analysis, it has been observed that, sub-threshold slope (SS) increases with the temperature more rapidly than kT/q, representing the paraelectric effect, and surpasses kT/q after 450 K and 500 K for SG-NCFET and HDDP-DG-NCFET, respectively. Furthermore, it has been observed that the impact of temperature variation is greater on the switching ratio of the device in the presence of trap charges, while the opposite is valid for the OFF current. Finally, it is found that the Gaussian distribution of traps worsen the SS characteristics and ON-OFF current ratio of the device severely as compared to the uniform distribution of traps.

Impact of Ag doping on subthreshold conduction in amorphous Ga2Te3 with threshold switching

Threshold switching devices with Ag-doped amorphous chalcogenides show enhanced threshold switching characteristics of a high selectivity and a low current in the subthreshold region. However, the mechanism underlying the decrease in this subthreshold current caused by Ag doping is not well understood. In this study, the effects of Ag doping in amorphous Ga 2 Te 3 are investigated in terms of the change in bonding structure and localized states in conjunction with threshold switching characteristics. X-ray photoelectron and Raman spectroscopies reveal the formation of Ag–Te bonds with a reduction in the amount of Te–Te bonds in Ga 2 Te 3 . In addition, the UV absorption shows an increase in the optical bandgap and a decrease of Urbach energy with Ag doping. The subthreshold current of the Ag-doped Ga 2 Te 3 device decreases by a factor of seven, and accordingly, the selectivity increases with respect to that of the undoped device. In addition, analyzing on the subthreshold conduction with a thermally assisted hopping model demonstrates a decrease in the density of localized states. Thus, the enhanced threshold switching characteristics of Ag-doped Ga 2 Te 3 are associated with the reduction of Te-induced localized states and the formation of Ag–Te bonds. • Excellent threshold switching characteristics of Ag-doped Ga 2 Te 3 thin films with various Ag doping concentrations. • The bonding structure was affected as Ag-Te bonding was formed with increasing Ag doping concentration. • The optical bandgap and localized states were significantly affected by Ag doping. • Extremely low off current of Ag-doped chalcogenide is correlated to the bonding structure, bandgap and localized states.

An Accurate Low-Power Power-on-Reset Circuit in 55-nm CMOS Technology

In this brief, an accurate low-power power-on-reset circuit is proposed. In order to get an accurate trip-voltage with little overhead, a low-power architecture based on current reference and current comparator is proposed. The reference current in the proposed power-on-reset circuit is mainly provided by the sub-threshold current of several native NMOS transistors, and a stable hysteresis window can be obtained by adjusting the number of enabled native NMOS transistors. Measurement results based on 55nm CMOS process show that the proposed power-on-reset circuit consumes only 32nW at the supply voltage of 0.5V. The measured power-on-reset trip-voltage is 0.45V with a temperature coefficient of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$227~\mu \text{V}/^{\circ }\text{C}$ </tex-math></inline-formula> . Since the proposed power-on reset circuit consists of only 10 transistors, the area of the proposed power-on-reset circuit is as low as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$67.5~\mu \text{m}^{2}$ </tex-math></inline-formula> .

Performance analysis of silicon nanotube dielectric pocket Tunnel FET for reduced ambipolar conduction

This work presents a novel structure of Nanotube Tunnel FET in which a high-k dielectric pocket is placed at the drain side to improve DC performance of the device. Using 3D TCAD simulation, it is shown that when a dielectric pocket (DP) is inserted at partially scaled drain region of Nanotube Tunnel FET at channel-drain interface then tunneling width at the output tunneling interface attains a maximum value for an optimum length and diameter of DP (i.e., 30 and 3 nm, respectively) which eventually reduces the ambipolar current up to a large extent. Furthermore, the subthreshold leakage current is also found to be reduced with the inclusion of DP in Nanotube Tunnel FET, thereby improving the current switching ratio (ION/IOFF). Additionally, the impact of varying k-value of DP on various DC parameters of the proposed device is demonstrated in this work and it is found that DP with high k-value reduces the ambipolar and subthreshold leakage current more as compared to the low-k DP. Moreover, the inclusion of DP dose not degrade the ON-state performance of Nanotube Tunnel FET as it has no significant impact on the rate of charge carriers tunneling through channel-drain interface during On-state.

Patch-Clamping Fly Brain Neurons.

The membrane potential of excitable cells, such as neurons and muscle cells, experiences a rich repertoire of dynamic changes mediated by an array of ligand- and voltage-gated ion channels. Central neurons, in particular, are fantastic computators of information, sensing, and integrating multiple subthreshold currents mediated by synaptic inputs and translating them into action potential patterns. Electrophysiology comprises a group of techniques that allow the direct measurement of electrical signals. There are many different electrophysiological approaches, but, because Drosophila neurons are small, the whole-cell patch-clamp technique is the only applicable method for recording electrical signals from individual central neurons. Here, we provide background on patch-clamp electrophysiology in Drosophila and introduce protocols for dissecting larval and adult brains, as well as for achieving whole-cell patch-clamp recordings of identified neuronal types. Patch clamping is a labor-intensive technique that requires a great deal of practice to become an expert; therefore, a steep learning curve should be anticipated. However, the instant gratification of neuronal spiking is an experience that we wish to share and disseminate, as many more Drosophila patch clampers are needed to study the electrical features of so many fly neuronal types unknown to date.

A discrete Huber-Braun neuron model: from nodal properties to network performance.

The online version contains supplementary material available at 10.1007/s11571-022-09806-1.

Investigating the effect of noisy galvanic vestibular stimulation on somatosensory perception in healthy adults

It is well known that the vestibular system is an important sensory system used by the brain for postural control or human balance. To maintain postural control, the brain needs to integrate with other signals from the various sensory systems. The somatosensory system is one such sensory system. Evidence in healthy people suggests that Galvanic Vestibular Stimulation (GVS) has facilitatory effects on somatosensory perception such as touch. As GVS is uncomfortable, it is more feasible to deliver a new variant of GVS called noisy galvanic vestibular stimulation (nGVS) which delivers GVS with a sub-threshold weak current. Therefore, this research aims to investigate the effects of nGVS on somatosensory perception on foot in healthy adults. The findings will provide new insights for better understanding any somatosensory enhancement induced by nGVS on sensory perception on foot. It is assumed that this proposed study has a potential to expand our understanding of the links between the vestibular system and the somatosensory system by giving a detailed view of whether the vestibular system can influence processing within the somatosensory pathway, which is important for human balance. This subsequent research is the first step which will provide greater understanding of the effects of nGVS on balance and may help in developing a new treatment using nGVS for people with poor balance. In this presentation I will present the methodology how we are going to understand the links between vestibular and somatosensory system using nGVS behind ears and seeing its effect on sensory perception on foot.

5-nm Gate-All-Around Transistor Technology With 3-D Stacked Nanosheets

A comprehensive computational study of gate-all-around (GAA) devices with 3-D stacked silicon nanosheets (also known as nanoribbons or nanowires) is presented in this article. Technology development guidelines are provided for low-power applications in 5-nm CMOS technology node and beyond. The 3-D stacked nanosheet devices lower the subthreshold swing, drain-induced barrier-lowering, and subthreshold leakage current by up to 20.75%, 38.89%, and 88.53%, respectively, when compared to a silicon-on-insulator (SOI) FinFET with 5-nm physical gate length and identical silicon area at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DD}} = {0.6}$ </tex-math></inline-formula> V and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T} = {80}\,\,^{\circ }\text{C}$ </tex-math></inline-formula> . The voltage gain of a minimum-sized CMOS inverter is increased by up to 157% with the 3-D stacked nanosheet devices, thereby providing robust operation with wider noise margins when compared to the SOI-FinFET technology. Furthermore, by scaling the supply voltage to 0.49 V, the energy consumption of a CMOS inverter is reduced by 53.81% with the GAA 3-D stacked nanosheet devices while providing similar output transition speed when compared to the SOI-FinFET technology.

On-chip leakage current variation measurement using external-reference-free current-to-time conversion for densely placed MOSFETs

This paper proposes a time-domain leakage current measurement circuit that uses an external-reference-free current-to-time conversion. Our proposed current-to-time converter (CTC) utilizes a dual inverter-based conversion to provide a stable reference. We share the CTC among the devices under test (DUTs) for accurate characterization of variation. Our CTC, along with a tree-based switch structure, allows us to densely place and route the DUT transistors using a cell-based design flow similar to a digital circuit design. We demonstrate our circuit by measuring subthreshold leakage currents of 256 minimum sized nMOSFETs in a 65 nm bulk low-power CMOS process. We could successfully extract the variations in subthreshold coefficient and subthreshold leakage current at different temperatures. Our circuit is also robust to supply voltage fluctuation making the circuit suitable for accurate characterization of MOSFET parameters for subthreshold operation.

Compact analytical modeling of underlap gate stack graded channel junction accumulation mode junctionless FET in subthreshold regime

This paper presents the compact analytical model of underlap gate stack (GS) graded channel (GC) junction accumulation mode (JAM) junctionless (JL) FET. At first, a comparative analysis between the two different graded channel schemes and non-graded channel is performed based on ION, IOFF and ION/IOFF ratio. The scheme that yields the higher ION/IOFF ratio along with smaller IOFF, is adopted in the proposed JL FET for further analysis. The 2D analytical modeling of the GS-GC-JAM-JL FET deals with the determination of surface potential, threshold voltage, subthreshold drain current, DIBL and subthreshold swing. Results obtained from analytical model and simulations are compared and an excellent match is found. Thus the present paper establishes the outstanding ability of proposed underlap GS-GC-JAM-JL FET architecture to shield the short channel effects without sacrificing its performance, and therefore, proves it as a potential candidate for ultra-low power applications.

Analytical model of subthreshold drain current for nanoscale negative capacitance junctionless FinFET

In this article, an analytical Subthreshold Drain Current model has been developed for Negative Capacitance Junctionless FinFET (NC-JL FinFET). To obtain the subthreshold current model for NC-JL FinFET the drift-diffusion equation is solved by including negative capacitance effect through LK equation and further utilized to attain the expression of subthreshold slope (SS). The influence of the fringing field due to source/drain spacer on the subthreshold current has been included in the model. The model predictions turn out to be in fair agreement with numerical simulation results. The performance of NC-JL FinFET is also examined for different technology nodes. Also, the influence of physical parameters like ferroelectric thickness, gate dielectric constant, fin thickness, spacer length etc. has also been analyzed. Further, the SS is also examined for variations in several device design parameters. It has been revealed that the NC-JL FinFET improves subthreshold current and SS by almost 80% and 16.7%, respectively as compared to JL FinFET.

Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs

Electronic system components can fall prey to counterfeiting via untrustworthy parties in the semiconductor supply chain, which has established a worldwide span to reduce costs, time to market, and increase productivity. Recently, integrated circuits (ICs) counterfeiting has threatened systems security and reliability that utilize ICs in all domains. This article focuses on the most counterfeited area—recycled and remarked ICs—and aims to develop a technique to distinguish between new and used digital ICs based on an aging sensor mechanism. Aging sensors have been studied based on path-delay fingerprinting and ring oscillators (ROs) frequency degradation, but their resolution requires further development to accurately detect short usage. This study proposes a novel differential aging sensor to measure the discharge time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\tau {{{dv}}}$ </tex-math></inline-formula> ) increase that depends on the subthreshold leakage current due to aging with two on-chip designs. Simulations were conducted using the GlobalFoundries (GF) 22 nm for aging with bias temperature instability and hot carrier injection (HCI) combined. The results show that the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\tau {{{dv}}}$ </tex-math></inline-formula> increase is 14.72% after 15 days of usage and increases to 60.49% after three years. This further increases at higher temperatures; the highest simulated temperature ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$125~^{\circ }\text{C}$ </tex-math></inline-formula> ) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\tau {{{dv}}}$ </tex-math></inline-formula> increases by 55.93% after 15 days and 310.17% after three years. The proposed method also outperformed the traditional frequency degradation-based aging estimation method, which at nominal temperature is found to be 5.00% after 15 days and 23.68% after three years. Therefore, discharge time is a sensitive indicator for aging, surpasses frequency in detecting previous usage and is robust against process, voltage, and temperature variations (PVTs).

Magnetic sensitivity modeling of dual gate MOS transistor

In this paper, the magnetic field effect on the carrier transport phenomenon in the double gate metal-oxide-semiconductor field-effect transistor (MOSFET) has been investigated. This is done by exploring the Lorentz force and the behavior of a semiconductor subjected to a constant magnetic field. The magnetic field modulates the electrons position and density as well as the potential distribution in the case of silicon tunnel tunneling field-effects (FETs). This modulation impacts the device electrical characteristics such as ON current (I&lt;sub&gt;ON&lt;/sub&gt;), subthreshold leakage current (IOF), threshold voltage (V&lt;sub&gt;T&lt;/sub&gt;), magneto-transconductance (g&lt;sub&gt;mm&lt;/sub&gt;) and output magneto-conductance (gm&lt;sub&gt;DS&lt;/sub&gt;). In addition, a hall voltage (V&lt;sub&gt;H&lt;/sub&gt;) is induced and modulated by the magnetic field. It has been observed that this voltage influences the effective applied gate voltage. It has been observed that the threshold voltage variations induced by the magnetic field is of paramount importance and affects the device switching properties both speed and power dissipation, noted that the threshold voltage VT and (Ion/Iof) ratio are reduced by 10&lt;sup&gt;-3&lt;/sup&gt;V and 10&lt;sup&gt;2&lt;/sup&gt; for a magnetic field of ±6 and ±5.5 Tesla, respectively. We have simulated the different behavior in the channel, mainly doping concentration, potential distribution, conduction and valence bands, total current density, total charge density, electric field, electron mobility, and electron velocity.

Performance Analysis of Dual Material Junction Accumulation Mode tri gate Junctionless SOI FET: Modeling and Simulation

The paper illustrates the performance of Tri-Gate (TG) Dual Material (DM) SOI (Silicon on Insulator) Junctionless (JL) FET operating in Junction Accumulation Mode (JAM). An analytical model is developed to evaluate its performance. The device is also simulated using Silvaco device simulator. Both the analytical and simulation results are compared and found to match closely. Quasi 3-D modeling approach is adopted here to determine the surface potential of the above device. In this technique, the entire 3-D device is segregated into two 2-D devices with certain physical constraints. These 2-D devices are then analyzed separately to obtain the surface potentials, which are added together using suitable multiplication factors to get the surface potential of the 3-D device. This surface potential is, in turn, used to model the threshold voltage, sub-threshold drain current (Id,sub) and the drain induced barrier lowering (DIBL). The proposed device configuration reduces the IOFF significantly and offers excellent immunity to SCEs. The response of the proposed device is studied for the variations of certain device parameters, such as, thickness of High-K dielectric layer in stack gate, channel doping, and the work-functions as well as lengths of the gate metals. Such study will lead to turn the proposed device immune to short channel effects through proper choice of various parameters.

The Immediate and Short-Term Effects of Transcutaneous Spinal Cord Stimulation and Peripheral Nerve Stimulation on Corticospinal Excitability.

Rehabilitative interventions involving electrical stimulation show promise for neuroplastic recovery in people living with Spinal Cord Injury (SCI). However, the understanding of how stimulation interacts with descending and spinal excitability remain unclear. In this study we compared the immediate and short-term (within a few minutes) effects of pairing Transcranial Magnetic Stimulation (TMS) with transcutaneous Spinal Cord stimulation (tSCS) and Peripheral Nerve Stimulation (PNS) on Corticospinal excitability in healthy subjects. Three separate experimental conditions were assessed. In Experiment I, paired associative stimulation (PAS) was applied, involving repeated pairing of single pulses of TMS and tSCS, either arriving simultaneously at the spinal motoneurones (PAS0ms) or slightly delayed (PAS5ms). Corticospinal and spinal excitability, and motor performance, were assessed before and after the PAS interventions in 24 subjects. Experiment II compared the immediate effects of tSCS and PNS on corticospinal excitability in 20 subjects. Experiment III compared the immediate effects of tSCS with tSCS delivered at the same stimulation amplitude but modulated with a carrier frequency (in the kHz range) on corticospinal excitability in 10 subjects. Electromyography (EMG) electrodes were placed over the Tibialis Anterior (TA) soleus (SOL) and vastus medialis (VM) muscles and stimulation electrodes (cathodes) were placed on the lumbar spine (tSCS) and lateral to the popliteal fossa (PNS). TMS over the primary motor cortex (M1) was paired with tSCS or PNS to produce Motor Evoked Potentials (MEPs) in the TA and SOL muscles. Simultaneous delivery of repetitive PAS (PAS0ms) increased corticospinal excitability and H-reflex amplitude at least 5 min after the intervention, and dorsiflexion force was increased in a force-matching task. When comparing effects on descending excitability between tSCS and PNS, a subsequent facilitation in MEPs was observed following tSCS at 30-50 ms which was not present following PNS. To a lesser extent this facilitatory effect was also observed with HF- tSCS at subthreshold currents. Here we have shown that repeated pairing of TMS and tSCS can increase corticospinal excitability when timed to arrive simultaneously at the alpha-motoneurone and can influence functional motor output. These results may be useful in optimizing stimulation parameters for neuroplasticity in people living with SCI.

Impact of an AlGaN spike in the buffer in 0.15 μm AlGaN/GaN HEMTs during step stress

On-wafer robustness and short-term reliability of 0.15 μm AlGaN/GaN HEMTs, fabricated on AlGaN buffer with a ‘mono-layer’ and c backbarrier between channel and buffer layers, have been compared. Results of DC characterization showed that devices with AlGaN ‘bi-layer’ backbarrier have better subthreshold behaviour, reduced on-resistance and leakage current, together with a slightly lower current and transconductance. Electroluminescence measurements suggested an increase of electric field in the ‘bi-layer’ devices. Observed failure modes are the following: (a) during off-state stress, threshold voltage shifts towards more negative values; (b) for semi-on and on-state tests, a non-monotonic threshold voltage instability, which initially becomes negative and then recovers is common to both types of devices; (c) during semi-on and on-state tests, a significant increase of RON occurs, which seems to be faster in devices without spike, despite the lower electric field suggested by EL measurements. Degradation of electrical characteristics has been attributed to the instability of charge on Carbon-related acceptor levels, enhanced by hot-electron effects.

The role of sodium channels in direct current stimulation-axonal perspective.

Transcranial neurostimulation methods are utilized as therapies for various neuropsychiatric disorders. Primarily, they entail the delivery of weak subthreshold currents across the brain, which modulate neuronal excitability. However, it is still a puzzle how such weak electrical fields actuate their effects. Previous studies showed that axons are the most sensitive subcellular compartment for direct current stimulation, and maximal polarization is achieved at their terminals. Nonetheless, polarization of axon terminals according to models was predicted to be weak, and the mechanism for substantial axon terminals polarization was obscure. Here, we show that a weak subthreshold electrical field modifies the conductance of voltage-dependent sodium channels in axon terminals, subsequently amplifying their membrane polarization. Moreover, we show that this amplification has substantial effects on synaptic functioning. Finally, we employ analytical modeling to explain how sodium currents modifications enhance axon terminal polarization. These findings relate to the mechanistic aspects of any neurostimulation technique.

Electrophysiological and Morphological Features of Rebound Depolarization Characterized Interneurons in Rat Superficial Spinal Dorsal Horn.

Substantia gelatinosa (SG) neurons, which are located in the spinal dorsal horn (lamina II), have been identified as the “central gate” for the transmission and modulation of nociceptive information. Rebound depolarization (RD), a biophysical property mediated by membrane hyperpolarization that is frequently recorded in the central nervous system, contributes to shaping neuronal intrinsic excitability and, in turn, contributes to neuronal output and network function. However, the electrophysiological and morphological properties of SG neurons exhibiting RD remain unclarified. In this study, whole-cell patch-clamp recordings were performed on SG neurons from parasagittal spinal cord slices. RD was detected in 44.44% (84 out of 189) of the SG neurons recorded. We found that RD-expressing neurons had more depolarized resting membrane potentials, more hyperpolarized action potential (AP) thresholds, higher AP amplitudes, shorter AP durations, and higher spike frequencies in response to depolarizing current injection than neurons without RD. Based on their firing patterns and morphological characteristics, we propose that most of the SG neurons with RD mainly displayed tonic firing (69.05%) and corresponded to islet cell morphology (58.82%). Meanwhile, subthreshold currents, including the hyperpolarization-activated cation current (Ih) and T-type calcium current (IT), were identified in SG neurons with RD. Blockage of Ih delayed the onset of the first spike in RD, while abolishment of IT significantly blunted the amplitude of RD. Regarding synaptic inputs, SG neurons with RD showed lower frequencies in both spontaneous and miniature excitatory synaptic currents. Furthermore, RD-expressing neurons received either Aδ- or C-afferent-mediated monosynaptic and polysynaptic inputs. However, RD-lacking neurons received afferents from monosynaptic and polysynaptic Aδ fibers and predominantly polysynaptic C-fibers. These findings demonstrate that SG neurons with RD have a specific cell-type distribution, and may differentially process somatosensory information compared to those without RD.

A Novel Method to Control Leakage and Noise in Domino Circuit for Wide Fan-In OR Logic

This paper proposes a novel method to control leakage and noise in domino circuits for wide fan-in OR logic with low power consumption, low process variation, and higher noise margin under the similar delay condition. In the proposed method, output and dynamic nodes are isolated from the PDN (Pull-Down Network) to improve the noise immunity and reduce switching activity. Further, with the aid of a transistor in the stack, the sub-threshold current is reduced. Thus, the proposed domino is applicable for high-speed and low-power applications in deep sub-micro-range. Simulation results show that the proposed domino improves the noise immunity and figure of merit (FOM) by factors of 1.95 and 2.34, respectively, with respect to the conventional domino with a footer. Along with this improvement, 26% reduction is also observed in power consumption. The entire simulations for all the domino circuits are done at 45-nm CMOS technology by using SPECTRE simulator under the Cadence Virtuoso environment.