An Accurate Low-Power Power-on-Reset Circuit in 55-nm CMOS Technology

Abstract

In this brief, an accurate low-power power-on-reset circuit is proposed. In order to get an accurate trip-voltage with little overhead, a low-power architecture based on current reference and current comparator is proposed. The reference current in the proposed power-on-reset circuit is mainly provided by the sub-threshold current of several native NMOS transistors, and a stable hysteresis window can be obtained by adjusting the number of enabled native NMOS transistors. Measurement results based on 55nm CMOS process show that the proposed power-on-reset circuit consumes only 32nW at the supply voltage of 0.5V. The measured power-on-reset trip-voltage is 0.45V with a temperature coefficient of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$227~\mu \text{V}/^{\circ }\text{C}$ </tex-math></inline-formula> . Since the proposed power-on reset circuit consists of only 10 transistors, the area of the proposed power-on-reset circuit is as low as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$67.5~\mu \text{m}^{2}$ </tex-math></inline-formula> .