Substrate Leakage Current Research Articles

Buried power rail to suppress substrate leakage in complementary field effect transistor (CFET)

Abstract In the pursuit of minimizing the track height in standard cell, a design innovation incorporating complementary field-effect transistors (CFETs) and Buried Power Rail (BPR) technology has been introduced. As the track height in conventional standard cells scales down to 3-track standard cell, the distance in-between the BPR metal and the bottom parasitic channel is required to be 13 nm or narrower. Consequently, a strong lateral electric-field, induced by the
BPR, is applied to the substrate parasitic channel, resulting in a substrate leakage current. To address this issue, various materials for barrier/liner in the BPR structure are explored and evaluated using TCAD simulation. It turned out that the BPR-induced field effect was suppressed as the dielectric constant of the barrier material and the work function of TiN liner decreased. The proposed BPR structure demonstrates the potential to mitigate device leakage current without increasing the doping concentration in substrate.

Manufacturing and characterization of CMOS-MEMS magnetic field microsensors with isolated cavities

The study investigates a magnetic field (MF) microsensor with isolated cavities manufactured utilizing complementary metal oxide semiconductor (CMOS)-microelectromechanical system technology. This microsensor, which is a type of magnetic transistor, comprises four identical magnetic sensing elements, each featuring an emitter, a base, two collectors, and an additional collector. The magnetic transistor operates on the principles of the Lorentz force. This force is employed to modulate the electrical properties of the transistor, responding to changes in the surrounding MF. The MF microsensor chip is fabricated using the commercial CMOS process. Upon completing the CMOS process, post-processing is employed to etch the silicon substrate of the microsensor chip, generating isolated cavities on the silicon substrate. These isolated cavities effectively mitigate substrate leakage current, enhancing the sensitivity of the MF microsensor. The experimental results reveal that the sensitivity of the microsensor without isolated cavities is 60 mV T−1. In contrast, the microsensor with isolated cavities exhibits a sensitivity of 121 mV T−1. A comparison between microsensors with and without isolated cavities depicts that the sensitivity of the MF microsensor with isolated cavities doubled.

The Development of Monolithic Silicon Carbide Intracortical Neural Interfaces for Long-Term Human Implantation

Silicon Carbide (SiC) has been demonstrated as both a bio- and neuro-compatible wide-band-gap semiconductor with a high thermal conductivity and magnetic susceptibility and may be potentially compatible with human brain tissue. Two single-crystal, solid-state forms of SiC have been used to create monolithic intracortical neural implants (INI) without using physiologically exposed metals or polymers, thus eliminating many known reliability challenges in-vivo through a single, homogenous material. Amorphous SiC (a-SiC) was used to insulate 16-channel functional INI and the electrochemical and MRI compatibility (7T) performance were measured. 4H-SiC interfaces were fabricated using homoepitaxy,alternating epitaxial films of n-type and p-type forming an isolating PN junction which prevents substrate leakage current between the 16 adjacent electrodes and traces fabricated which were formed using deep-reactive ion etching (DRIE). 3C-SiC interfaces were fabricated in a similar fashion, but the epitaial conductive layers were grown on on both bulk crystalline (100) silicon and SOI wafers. In both cases a conformal coating of a-SiC was used as the top-side insulator and windows opened using RIE to allow electrochemical interaction. Electrochemical charaterization achieved through electrochemcial impedance spectroscopy (EIS) and cyclic voltammetry (CV) indicates performance on par, or exceeding, that of Pt reference electrodes with the same form fit. While magnetic resonance imaging (MRI) is an essential, non-contact method used to investigate issues with the nervous system, the high field MRI (e.g., 3 T and higher) necessary for proper diagnosis can be a safety issue for patients with INI due to inductive coupling between the powerful electromagnetic fields and the implanted device. This results in having to use lower electromagnetic field power (less than 1.5T), and therefore lower resolution, which hinders diagnostic prognosis for these patients. In this work the MRI compliance of epitaxial, monolithic SiC INI was studied. The specific absorption rate (SAR), induced heating, and image artifacts caused by the portion of the implant within a brain tissue phantom located in a 7 T small animal MRI machine were estimated and measured via finite element method (FEM) and Fourier-based simulations. Both the simulation and experimental results revealed that free-standing 3C-SiC films had no observable image artifacts compared to silicon and platinum reference materials inside the MRI at 7 T while FEM simulations predicted an ~30% SAR reduction for 3C-SiC compared to Pt. These initial simulations and experiments indicate a SiC monolithic INI may effectively reduce MRI induced heating and image artifacts in high field MRI.

A Π-shaped p-GaN HEMT for reliable enhancement mode operation

This paper presents a TCAD based investigation of virtually fabricated Π-shaped Gate p-GaN HEMT for reliable enhancement mode operation. A detailed comparison with the Conventional T-Gate counterpart, with a focus towards the trap related dispersive effect reveals the superiority of Π-shaped Gates P-GaN HEMT for suppressing both the vertical substrate and gate leakage currents, thereby enhancing the breakdown characteristics of the device. A modification of the electric fields, into a stepped profile, demonstrates effective suppression of the leakage through the surface defects, and spillover into GaN buffer, thereby mitigating the trap related dispersive effects. Dispersive effect of the two devices has also been compared using current Slump Ratio (SR) which is lower for Π-shaped Gate P-GaN HEMT. Further analysis into laterally scaled drain-access regions, demonstrates superiority of Π-shaped Gates in achieving a reliable thermal operation, and applicability of Π-shaped Gate P-GaN HEMT for future RF and High Power applications.

Optimized Substrate for Improved Performance of Stacked Nanosheet Field-Effect Transistor

The recently proposed stacked nanosheet-field-effect transistor (SNSH-FET) is considered as a promising candidate for continued scaling with silicon. While using punchthrough-stopper-doped (or) ground-plane-doped silicon substrate (PTS-Si substrate) in which the top part of the substrate is doped heavily with the p-type (for nMOS) impurity to avoid punchthrough leakage between the source and the drain. The heavily doped p–n junction formed at the drain–substrate junction acts as a reverse-biased tunnel diode during ${V}_{{\text {DS}}}$ biasing, which leads to large substrate leakage current. We presented SuperSteep-Retrograde silicon substrate (SSR-Si substrate) configuration which reduces the tunneling current by increasing the tunnel barrier width and diminishing the peak electric field at the drain–substrate junction. The SSR-Si substrate is achieved by growing a lightly doped or undoped layer of silicon (SSR-buffer layer) on the PTS-doped substrate. The impact of SSR-buffer layer thickness is studied and the optimal thickness (12 nm) is presented. The vertically stacked channels’ configuration leads to position-dependent current densities in different channels due to position-dependent series resistance. Herein, we present nanosheet width optimization as a solution to achieve homogeneous current ratio between all the channels thereby resulting in better linearity performance. The self-heating and RF performance of the presented SSR-Si substrate is compared with the silicon-on-insulator (SOI) substrate. The results show that SSR-Si substrate can be a better substrate for SNSH-FET because of better self-heating performance.

On the impact of substrate electron injection on dynamic Ron in GaN-on-Si HEMTs

The impact of electron injection from the substrate on the dynamic Ron of GaN-on-Si High Electron Mobility Transistors (HEMTs) has been investigated by means of back-bias transient and vertical leakage measurements and TCAD simulations. A strong correlation between electrons injected from the substrate and on-state drain current transients is demonstrated. Moreover, the contribution of the electron-type traps in the buffer layer as opposed to the usually studied hole-like traps to the dynamic Ron is discussed. In particular, the impact of electron-like traps for different levels of substrate leakage current is studied. A TCAD model has been developed and calibrated by taking into account both off-state vertical leakage and on-state drain current transient experimental results. The proposed charge dynamic has also been assessed against state-of-the-art theories. This analysis contributes to a deeper understanding of the complex scenario of different types of traps in the buffer layer of GaN-on-Si devices and highlights the impact that trap-states can have on the on-state and off-state currents.

Leakage compensation scheme for ultra‐high‐resistance pseudo‐resistors in neural amplifiers

Although MOS-based pseudo-resistors are capable of achieving the ultra-high resistance required to design small-area neural amplifiers, they suffer from substrate leakage currents which become dramatically higher when the devices are exposed to light. This can cause unwanted amplifier offsets and hinders the usability of these devices in the emerging optoelectrical neural applications. A solution is proposed to compensate the pseudo-resistor leakage current using a dummy deep N-well device. Experimental results show that neural amplifiers implemented with the compensated pseudo-resistor become more robust to photo-induced leakage currents.

Design and development of a novel MOSFET structure for reduction of reverse bias pn junction leakage current

Present world is acquainted with the plethora of battery operated portable electronic goods in leaps and bounds. For long life of battery, it is very imperative to minimise the leakage current in devices. Amount of leakage in scaled deep-submicron VLSI1 CMOS circuitry has already occupied a momentous part of the total power consumption, and likely to amplify in future with technology scaling. Top three dominant components of transistor leakage current are gate leakage, subthreshold leakage and p-n junction leakage. We report our study of constructional modification of MOSFET transistor to control p-n junction leakage current. TCAD simulation was performed on a 20 nm NMOS, following the rules of International Technology Roadmap for Semiconductors (ITRS). As substrate is the common terminal for this kind of leakage, substrate current was measured to note the effectiveness of the proposed methodology. A 52% reduction in substrate leakage current was noted after applying the proposed methodology.

An On-Chip Multi-Voltage Power Converter With Leakage Current Prevention Using 0.18 μm High-Voltage CMOS Process.

In this paper, we present an on-chip multi-voltage power converter incorporating of a quad-voltage timing-control rectifier and regulators to produce ±12 V and ±1.8 V simultaneously through inductive powering. The power converter achieves a PCE of 77.3% with the delivery of more than 100 mW to the implant. The proposed rectifier adopts a two-phase start-up scheme and mixed-voltage gate controller to avoid substrate leakage current. This current cannot be prevented by the conventional dynamic substrate biasing technique when using the high-voltage CMOS process with transistor threshold voltage higher than the turn-on voltage of parasitic diodes. High power conversion efficiency is achieved by 1) substrate leakage current prevention, 2) operating all rectifying transistors as switches with boosted gate control voltages, and 3) compensating the delayed turn-on and preventing reverse leakage current of rectifying switches with the proposed look-ahead comparator. This chip occupies an area of 970 μm × 4500 μm in a 0.18 μ m 32 V HV CMOS process. The quad-voltage timing-control rectifier alone is able to output a high DC voltage at the range of [2.5 V, 25 V]. With this power converter, both bench-top experiment and in-vivo power link test using a rat model were validated.

Measurement and analysis of substrate leakage current of RF mems capacitive switches

This paper focused on a new direction of study on leakage current called substrate charge injection. The substrate leakage current of capacitive RF micro-electro-mechanical-system (MEMS) switches was measured, and the conduction mechanism was estimated. The study of the leakage current conduction mechanisms of the substrate dielectric film shows that leakage is mainly induced by hopping conduction at low electric fields, whereas both Schottky emission and hopping conduction may contribute to the leakage current at high fields. The quantitative relationship between the substrate leakage current and the dielectric layer leakage current was also determined for the first time. In the case of low drive voltage (0–30V), the substrate leakage current significantly contributes to the total leakage current. Results show that the charging properties of the substrate should not be neglected at low drive voltage because such properties could significantly affect the functionality and reliability of RF MEMS switches.

The Study of Improving High Voltage LIGBT Substrate Leakage Current

This paper aims to the research of high voltage lateral insulated gate bipolar transistor (LIGBT) and proposes the design for reducing the substrate leakage current of this device. The junction between LIGBT’s p-type substrate and n-epi layer may have a large electrical field and causes the hole current to flow during the turn-on state. To prevent this substrate leakage current, an n-type buried layer (NBL) and a p-type buried layer (PBL) are used. The double reverse biased pn-junction structure effectively reduces the vertical electric field such that the substrate current is reduced by four orders of magnitude. The break down voltage of the LIGBT is not hurt by this added structure at all.

Analysis of Off-State Leakage Current Characteristics and Mechanisms of Nanoscale MOSFETs with a High-k Gate Dielectric

The off-state leakage current characteristics of nanoscale channel metal-oxide-semiconductor field-effect transistors with a high-k gate dielectric are thoroughly investigated. The off-state leakage current can be divided into three components: the gate leakage current, the source leakage current, and the substrate leakage current. The influences of the fringing-induced barrier lowering effect and the drain-induced barrier lowering effect on each component are investigated separately. For nanoscale devices with high-k gates, the source leakage current becomes the major component of the off-state leakage current.

Three-dimensional Monte Carlo simulation of bulk fin field effect transistor

In this paper, we investigate the performance of the bulk fin field effect transistor (FinFET) through a three-dimensional (3D) full band Monte Carlo simulator with quantum correction. Several scattering mechanisms, such as the acoustic and optical phonon scattering, the ionized impurity scattering, the impact ionization scattering and the surface roughness scattering are considered in our simulator. The effects of the substrate bias and the surface roughness scattering near the Si/SiO2 interface on the performance of bulk FinFET are mainly discussed in our work. Our results show that the on-current of bulk FinFET is sensitive to the surface roughness and that we can reduce the substrate leakage current by modulating the substrate bias voltage.

Negative voltage level shift in clamping circuits for passive wireless microsystems

Negative voltage level shift in voltage clamping circuits is proposed to design a low-power negative voltage level shifter converting unipolar voltage levels to dual-polarity voltages and to design a negative voltage doubler (multiplier) with reduced substrate leakage currents. The negative voltage level shifter stabilizes its output voltage levels by a current compensation path. And the negative voltage doubler employs diode-connected PFETs for the substrate leakage current suppression. Designed in IBM 0.13-μm CMOS technology and analyzed with BSIMv4.4 device models, the power consumption of the proposed negative voltage level shifter is just a few tens of nWs. And the substrate leakage current of the proposed PFET negative voltage doubler can be reduced to nA ranges from μA ranges of its NFET counterparts.

Fluorine passivation of vacancy defects in bulk germanium for Ge metal-oxide-semiconductor field-effect transistor application

Vacancy defects in germanium (Ge) adversely impact the electrical performance of Ge based metal-oxide-semiconductor field-effect transistor (MOSFET) in several ways. They behave as an acceptor site, thereby deactivating n-type dopants in the source/drain region. They can also increase substrate leakage currents and impact carrier lifetime in the channel region. In this paper, we characterize and verify the electrical behavior of vacancy defects in Ge using spreading resistance profiling (SRP). Effect of thermal annealing on the vacancy concentration is studied. Finally, passivation of these defects using fluorine (F) ion-implant is shown to demonstrate the feasibility of performance enhancement in Ge-MOSFETs.

Low substrate-current and high breakdown voltage JI-LIGBT

A novel bulk junction isolated lateral insulated gate bipolar transistor (JI-LIGBT) with a heavily doped buried-layer in substrate is presented. Due to electric field modulation and current-gain reduction of the vertical parasitic transistor from the buried-layer, in comparison with the conventional LIGBT without a buried-layer, the novel structure offers not only high breakdown voltage but also short turn-off time and significantly low substrate leakage current.

Low-frequency noises in GaAs MESFET’s currents associated with substrate conductivity and channel-substrate junction

Low-frequency noises in GaAs MESFET are usually observed when investigating the drain current and substrate leakage current under sidegate bias conditions. Experimental results show that the magnitude of low-frequency noises is in a direct dependency upon the sidegate bias and the noises in drain current will disappear if sidegate bias increases more negatively beyond a certain voltage. A mechanism associated with the substrate conductivity and the channel-substrate junction modulated by sidegate bias is proposed to explain the fluctuation of low-frequency noises.

Modeling of substrate leakage currents in a high-voltage CMOS rectifier

In high-voltage (HV) CMOS integrated circuits (ICs), substrate leakage currents are important design considerations as they increase power consumption and the risk of latch-up. In safety critical applications, such as in biomedical implants, the problem is particularly important. Unfortunately, substrate leakage current paths are mainly formed by semiconductor process parasitic components, which are difficult to analyze accurately by SPICE schematic simulations. This paper presents a realistic modeling work about the substrate leakage currents in implantable HV ICs. As a case study, a rectifier prototype has been implemented in a 0.35-μm HV CMOS process. The simulations based on the models show good agreement with measurements on the experimental prototype.

Improved performance of GaAs-based micro-solar cell with novel polyimide/SiO2/TiAu/SiO2 structure

A novel interconnected structure consisting of a conventional polyimide layer (PM) and an additional SiO2/TiAu/SiO2 sandwich multilayer has been firstly proposed for improving the performance of GaAs micro-solar cell array. The specific experimental investigations on the array with 108 unit cells have demonstrated that the novel structure of PM/SiO2/TiAu/SiO2 can effectively enhance the open-circuit voltage from 75 to 84 V and the fill factor from 35% to 57%. The performance improvement of our devices can be attributed to two aspects. Firstly, the TiAu shielding film can prevent the incident light from penetrating into the GaAs substrate so as to induce the serious substrate leakage current. Secondly, the compact texture of SiO2 in the novel structure can reduce the perimere recombination due to the crackle or shrinkage of PM. It is indicated that the novel structure can distinctly reduce the leakage current and improve output characteristic of micro-solar cells.

Analysis of Inductive Coupling and Design of Rectifier Circuit for Inter-Chip Wireless Power Link

A wireless power link utilizing inductive coupling is developed between stacked chips. In this paper, we discuss inductor layout optimization and rectifier circuit design. The inductive-coupling power link is analyzed using simple equivalent circuit models. On the basis of the analytic models, the inductor size is minimized for the given required power on the receiver chip. Two kinds of full-wave rectifiers are discussed and compared. Various low-power circuit design techniques for rectifiers are employed to decrease the substrate leakage current, reduce the possibility of latch-up, and improve the power transmission efficiency and the high-frequency performance of the rectifier block. Test chips are fabricated in a 0.18µm CMOS process. With a pair of 700 × 700µm2 on-chip inductors, the test chips achieve 10% peak efficiency and 36mW power transmission. Compared with the previous work the received power is 13 times larger for the same inductor size [7].