Abstract
Negative voltage level shift in voltage clamping circuits is proposed to design a low-power negative voltage level shifter converting unipolar voltage levels to dual-polarity voltages and to design a negative voltage doubler (multiplier) with reduced substrate leakage currents. The negative voltage level shifter stabilizes its output voltage levels by a current compensation path. And the negative voltage doubler employs diode-connected PFETs for the substrate leakage current suppression. Designed in IBM 0.13-μm CMOS technology and analyzed with BSIMv4.4 device models, the power consumption of the proposed negative voltage level shifter is just a few tens of nWs. And the substrate leakage current of the proposed PFET negative voltage doubler can be reduced to nA ranges from μA ranges of its NFET counterparts.
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