Substrate Leakage Current Research Articles

Influence of the Ge concentration in the virtual substrate on the low frequency noise in strained-Si surface n-channel metal-oxide-semiconductor field-effect transistors

We report on low frequency noise and field-effect mobility in strained-Si surface n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) grown on relaxed virtual substrates with a Ge concentration varying between 0% and 30%. An increased Ge concentration results in higher intrinsic field-effect mobility, increasing from 380cm2V−1s−1 for the unstrained channel to 865cm2V−1s−1 for the strained-Si MOSFET on 30% relaxed SiGe virtual substrate. However, the higher mobility is traded off for increased substrate leakage currents and increased 1∕f (flicker) noise. It is suggested that flicker noise is due to traps in the oxide layer. The density of traps increases from 2×1017eV−1cm−3 for 0% Ge to 2.3×1018eV−1cm−3 for the 30% Ge virtual substrate.

Hot-Carrier Reliability and Analog Performance Investigation of DMG-ISEGaS MOSFET

Dual-material-gate (DMG) insulated shallow extension gate-stack MOSFET involving dielectric pocket (DP) and DMG assimilation onto the conventional MOSFET has been studied. Simulations reveal a reduction in substrate leakage current, linearity improvement, enhancement in - g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> , early voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EA</sub> ), and g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> , down to 50-nm gate length as an outcome of this DP and DMG integration.

DC Performance of Deep Submicrometer Schottky-Gated n-Channel Si:SiGe HFETs at Low Temperatures

N-type Schottky-gated Si:SiGe heterostructure field-effect transistors with physical gate lengths between 70 and 450nm are characterized over a wide temperature range (T=10 K...300 K) for low electric fields. The room-temperature maximum low-field transconductance increases 61% to 440 mS/mm at T=10 K for the 70-nm device. The minimum subthreshold slope is 14...19 mV/dec at T=10 K. The off-state currents I/sub OFF/ are limited by parallel conduction at high temperatures and by the gate leakage current at low temperatures. Substrate leakage currents are found to be due to generation of carriers within the drain/substrate depletion layer and only make a minor contribution to I/sub OFF/. Operation of the devices at the lowest temperature is found to result in the occurrence of the floating-body kink effect, as a consequence of substrate freeze-out and subsequent self-biasing by impact ionization currents. Low temperature characteristics exhibit a nonlinear low-field drain current dependence on the drain voltage, due to the presence of parasitic Schottky source/drain contacts. An extraction method for access resistance consistent with this phenomenon is presented.

High-Purity Versus High-Defect-Density Semiinsulating Substrates for SiC MESFET: Simulation of Device Characteristics

Quantitative assessment of the influence of deep traps in semiinsulating (SI) SiC substrates on transient behavior and substrate leakage current of SiC MESFET is reported. Twodimensional device simulation confirmed that favorable reduction of the current-collapse happens when a fully depleted buffer is used. Simultaneously, the high-purity buffer causes an undesirable increase of the current bypassing the physical channel. A similar and even more pronounced effect is observed when very high purity SI substrates are used. The deep level-induced transient behavior disappears for the concentration of deep acceptor traps below the order of 1x1015 cm-3. However, this low trap concentration results in a virtual inability to pinch-off the channel even at very high gate biases. It has been demonstrated that the electric field preventing electron injection from thechannel into the substrate is very sensitive to the initial charge state of the traps prior to device biasing, which in turn is determined by the energy position of the deep levels in the substrate.

Ion-implantation technology for improved GaAs MESFETs performance

Electrical properties of Si-implanted and co-implanted with Mg or Be in semi-insulating GaAs was studied. The Si-implanted MESFETs with and without buried p-layer (formed by Mg or Be) have been fabricated and characterized by their d.c. and r.f. performance. The experimental results showed that the device with a buried p-layer can effectively suppress the substrate leakage current (thus good pinch-off characteristic) and obtained higher gain linearity than these without a buried p-layer. For 1 μm×100 μm MESFETs device with co-implantation of Si (∼8×1012 cm−2) and Be (∼6×1011 cm−2) demonstrated uniform transconductance (gm) of ∼115 mS mm−1 with the gate voltage ranging from −1 to 1 V and reduced pinch-off voltage compared to those with co-implantation of Si and Mg (∼6×1011 cm−2). The measured fT and fmax of a 1 μm×25 μm MESFET with co-implantation of Si and Be are 10 and 39 GHz, respectively. However, FETs with increased Mg dose (from 6×1011 cm−2 to 2×1012 cm−2) in a buried p-layer can obtain higher transconductance and saturation current.

Low-leakage diode string designs using triple-well technologies for RF-ESD applications

This letter proposes a novel low-leakage diode string designs using triple-well technologies in 0.18-/spl mu/m CMOS process for RF-electrostatic discharge (RF-ESD) applications. Based on the characteristics of the low-leakage current and low-capacitance in the triple-well diode string, it is convenient to apply it in RF-ESD (electrostatic discharge) protection circuit designs. As compared to the conventional p/sup +//n-well diode string, the substrate leakage current can be kept very small all the time before the triple-well diode string turns on. It results from the existence of the parasitic base-emitter tied p-n-p bipolar transistor in each triple-well diode.

Characterization of soft breakdown in thin oxide NMOSFETs based on the analysis of the substrate current

We have investigated the properties of soft breakdown (SBO) in thin oxide (4.5 nm) nMOSFETs with measurements of the gate and substrate leakage currents using the carrier separation technique. We have observed that, at lower gate voltages, the level of the substrate current exhibits a plateau. We propose that the observed plateau is due to the Shockley-Hall-Read (SHR) generation of hole-electron pairs in the space charge region and at the Si-SiO/sub 2/ interface. At higher voltages, the substrate current steeply increases with voltage, due to a tunneling mechanism, trap-assisted or due to a localized effective thinning of the oxide, from the substrate valence band to the gate conduction band, which becomes possible for gate voltages higher than the threshold voltage. The proposed interpretation Is consistent with the results of measurements performed at different operating conditions, in the presence of light and in the case of substrate reverse bias. The presented results are also useful for characterizing the performance of MOSFETs after SBD.

Influence of the undoped spacer layer thickness on the DC characteristics of n-type GaAs/AlAs MESFETs

We have investigated the influence of the thickness of an undoped spacer layer under the channel on the current-voltage characteristics of GaAs MESFETs. To that purpose we have grown the active layers of the MESFETs on top of a 50 nm AlAs layer to separate the device effectively from the undoped GaAs substrate. Substrate leakage currents are of the order of A at 30 V source-substrate bias. DC characteristics are measured for four MESFETs with identical layer structure and doping but different spacer layer thicknesses. Comparison shows that MESFETs with thin spacer layers can be useful for low-noise applications but lose in transconductance and mobility values.

GaAs MESFET's on a truly insulating buffer layer: demonstration of the GaAs on insulator technology

We demonstrate for the first time a GaAs on insulator (GOI) technology, with aluminum oxide (Al/sub 2/O/sub 3/) formed by the wet oxidation of AlAs as the insulating buffer layer. The insulating buffer gives excellent charge control and eliminates substrate leakage current. The first results of GOI technology include 1.5-/spl mu/m gate length GOI MESFET's with f/sub /spl tau//=9 GHz and f/sub max/=45 GHz.

Numerical simulation of sidegating effect in GaAs MESFET's

Two-dimensional simulation of the sidegating effect in GaAs MESFETs has been performed. The result confirms that Schottky contacts on a semi-insulating substrate cause serious high substrate leakage current and drain current reduction in GaAs MESFETs. The threshold behavior in the sidegating effect is found to correlate with the conduction behavior of the Schottky-i-n (sidegate) structure when the sidegate is negatively biased. Shielding and enhancement of the sidegating effect by the Schottky contacts have also been studied, and the results agree with the experimental findings. Besides, the presence of hole traps in the semi-insulating substrate is found to be essential to the sidegating effect.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Numerical simulation of the hysteresis in the sidegating effect in GaAs MESFETs-the effect of Schottky contacts

Two-dimensional simulation of the sidegating effect in GaAs MESFETs has been performed. The result confirms that Schottky contacts on semi-insulating substrate cause serious high substrate leakage current and drain current reduction in GaAs MESFETs. The competition between the currents or biases of the contacts is found to be the cause of the S-type negative differential conductivity (S-NDC) or hysteresis observed when measuring the sidegating threshold. >

The PHOTOFET method in submicrometre GaAs MESFETS: substrate leakage current effect

The PHOTOFET method is applied to submicrometre MESFETS processed on ion-implanted Cr-doped substrates. It is demonstrated that the magnitude of the photoconductivity both under extrinsic and intrinsic illumination is determined by the substrate leakage current, which is a function of the device drain bias. A semiempirical modeling of the dependence of the photoconductivity on the device bias gives a power-law relation between the leakage current and the drain bias.

Characteristics including electron velocity overshoot for 0.1- mu m-gate-length GaAs SAINT MESFET's

Short-channel effects, substrate leakage current, and average electron velocity are investigated for 0.1- mu m-gate-length GaAs MESFETs fabricated using the SAINT (self-aligned implantation for n/sup +/-layer technology) process. The threshold-voltage shift was scaled by the aspect ratio of the channel thickness to the gate length (a/L/sub g/). The substrate leakage current in a sub-quarter-micrometer MESFET is completely suppressed by the buried p layers and shallow n/sup +/-layers. The average electron velocity for 0.1- to 0.2- mu m-gate-length FETs is estimated to be 3*10/sup 6/ cm/s from the analysis of intrinsic FET parameters. This high value indicates electron velocity overshoot. Moreover, a very high f/sub T/ of 93.1 GHz has been attained by the 0.1- mu m SAINT MESFET. >

A Novel Process for High‐Performance Schottky Barrier PMOS

A novel process for high‐performance rinsed asymmetric Schottky barrier PMOS transistors with a Schottky barrier junction source and a P‐N junction drain is proposed. is used to form the source Schottky junction. No spacer oxide is necessary for this process to isolate the poly‐Si gate and the source ; thus the source may directly contact the inverted channel. Measured results show that the new Schottky barrier PMOS can circumvent the drawback of the conventional Schottky barrier PMOS, such as low drain driving current, poor transconductance, and high drain to substrate leakage current.

A 630-mS/mm GaAs MESFET with Au/WSiN refractory metal gate

GaAs MESFET's with a gate length as low as 0.2 mu m have been successfully fabricated with Au/WSiN refractory metal gate n/sup +/-self-aligned ion-implantation technology. A very thin channel layer with high carrier concentration was realized with 10-keV ion implantation of Si and rapid thermal annealing. Low-energy implantation of the n/sup +/-contact regions was examined to reduce substrate leakage current. The 0.2- mu m gate-length devices exhibited a maximum transconductance of 630 mS/mm and an intrinsic transconductance of 920 mS/mm at a threshold voltage of -0.14 V.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Planar monolithic integration of LED and FET devices on a conductive substrate

This paper describes results of a study on the monolithic integration of AlGaAs light-emitting diodes with GaAs field-effect transistors on a conductive p-GaAs substrate. Using a selective growth technique, a horizontal configuration is fabricated that allows separate optimization of the two types of devices and provides a quasi-planar surface. This approach is compatible with the standard GaAs integrated-circuit technology. By inserting an undoped layer and a p-n junction between the active layer of the FET and the substrate leakage currents below 500 µA for bias voltage up to 9 V are obtained for these insulation structures. The emitted light intensity of the LED, connected in series with the FET, exhibits a nearly linear dependence on the driving gate potential. Temperature or optical crosstalk effects were not observed. Fall and rise times around 20 ns were measured from the pulse response characteristics. This switching time is limited by the LED whereas the FET and isolation layers were found not to affect the switching behavior of the circuit in this time frame.

The Effects of Proton Implant on GaAs Isolation Properties

The semi‐insulating property of and the backgating (or sidegating) effect are intimately related. Protons implanted at high energy have been demonstrated to reduce the backgating effect by damaging the crystal and, thus, creating electron traps. This damage process also has an impact on the isolation properties of the material. The isolation and backgating properties of the intrinsic material and proton implanted material, as a function of temperature and voltage, are measured and compared. Activation energies for substrate leakage current are calculated and reported.

Mechanisms for low-frequency oscillations in GaAs FET's

Low-frequency oscillations in GaAs MESFET's were observed under back-gating conditions. The FET oscillations are directly related to oscillations in leakage currents in the semi-insulating GaAs substrate. The occurrence of these oscillations in the substrate is strongly dependent upon GaAs material. It is proposed that oscillating substrate leakage currents modulate the FET current in two ways; first, by modulating the active channel-substrate junction and second, by inducing periodic voltage fluctuations on the gate via gate pad contacts on the semi-insulating substrate. The latter mechanism is dominant and dependent upon gate bias and gate impedance.

Sidegating in GaAs current limiters

Potentials of several volts or less applied to the sidegate contact of an ion-implanted GaAs current limiter cause a decrease in the channel current, in both the linear and Saturated modes of operation. Larger sidegate potentials have the opposite effect due to the addition of a large substrate leakage current, and cause an apparent shift in the impact-ionization threshold of the channel current.