Modeling of substrate leakage currents in a high-voltage CMOS rectifier

Abstract

In high-voltage (HV) CMOS integrated circuits (ICs), substrate leakage currents are important design considerations as they increase power consumption and the risk of latch-up. In safety critical applications, such as in biomedical implants, the problem is particularly important. Unfortunately, substrate leakage current paths are mainly formed by semiconductor process parasitic components, which are difficult to analyze accurately by SPICE schematic simulations. This paper presents a realistic modeling work about the substrate leakage currents in implantable HV ICs. As a case study, a rectifier prototype has been implemented in a 0.35-μm HV CMOS process. The simulations based on the models show good agreement with measurements on the experimental prototype.