Abstract
The dependence of device structures on latchup immunity in a 0.25-mum high-voltage (HV) 40-V CMOS process with drain-extended MOS (DEMOS) transistors has been verified with silicon test chips and investigated with device simulation. Layout parameters such as anode-to-cathode spacing and guard ring width are also investigated to find their impacts on latchup immunity. It was demonstrated that the drain-extended NMOS with a specific isolated device structure can greatly enhance the latchup immunity. The proposed test structures and simulation methodologies can be applied to extract safe and compact design rule for latchup prevention of DEMOS transistors in HV CMOS process
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