Submicrometer Gate Lengths Research Articles

Self-aligned-gate GaInAs microwave MISFET's

A self-aligned-gate GaInAs metal-insulator-semiconductor FET (MISFET) fabrication process that minimizes gate overlap capacitance and offers the potential of achieving submicrometer gate lengths is described. GaInAs MISFETs (1-µm gate length) fabricated with this process have given 0.49-W/mm gate width and corresponding power-added efficiencies of 48 and 39 percent at 4 and 8 GHz, respectively, at a drain voltage of 5.5. V. A small-signal gain of 3.2 dB was obtained at 15 GHz. The estimated carrier velocity was 1.7 × 107cm/s. More recent devices have carrier velocities of 2.5 × 107cm/s and are expected to have improved microwave performance.

Buried p-layer SAINT for very high-speed GaAs LSI's with submicrometer gate length

A new SAINT FET with a depleted p-layer buried under the active layer has been developed in order to make very high-speed GaAs LSI's with submicrometer gate lengths. The p-layer design has successfully suppressed the substrate current that causes the serious short-channel effects in an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> self-aligned (SAINT) MESFET. Since the whole p-layer, formed by Be ion implantation, is depleted by the built-in potential against the upper n-channel layer, it does not lead to a parasitic capacitance increase. The impurity concentration of the player has been limited to optimize operation speed. The alleviation of the short-channel effects combined with the reduction of effective channel thickness has increased the drain current by a factor of about 2 and decreased the propagation delay time of the ring oscillator by a factor of 1.6. A maximum transconductance of 420 mS/mm and a minimum delay time of 9.9 ps/gate have been obtained at room temperature.

A fully-scaled NMOS technology for VLSI circuits

A fully-scaled NMOS process was developed for VLSI cirsuits. Device isolation was achieved by channel stop implant using a reverse tone resist technique. This isolation process gives high field turn-on voltage, minimal narrow width effect and low body effect. A tri-level photoresist process was developed for gate definition. This process technology was demonstrated through the successful fabrication of an 8×8 bit parallel multiplier with submicrometer gatelengths. This 8×8 bit multiplier has a multiplication time of 9.5 ns.

Structure-enhanced MOSFET degradation due to hot-electron injection

Device degradation due to channel hot-electron injection in several nonconventional MOSFET structures including minimum-overlap gate, offset gate, graded drain, and lightly doped drain (LDD) structures are evaluated. In these nonconventional structures the device degradation is much faster than that in conventional devices when biased with the same amount of hot electrons in the channel. This faster degradation rate is proposed to be due to external channel pinchoff at the more lightly doped drain edge. This behavior implies even more severe constraints on the operating regime for these nonconventional device structures at submicrometer gatelengths to maintain adequate reliability margins.

The performance of submicrometer gate length GaAs MESFET's

The influence of gate length, active layer thickness, and buffer layer current upon the steady-state and RF parameters of short gate length GaAs MESFET's is investigated using a two-dimensional model that accounts for electron energy relaxation effects. For devices of similar pinchoff voltage, the saturation currents are approximately the same, but the presence of substrate conduction in a device greatly reduces its transconductance and gain-bandwidth product. The effect upon frequency response due to gate length, donor profile, gate resistance, and source inductance is numerically evaluated. The model is shown to be in reasonable agreement with measured submicrometer device characteristics.

Fabrication and analysis of 1/2µm Silicon logic MESFET's

Submicrometer gate length MESFET logic on silicon-on-sapphire (SOS) has been explored for very high-speed switching. The measured values for gate length, current drive capability, transconductance, output conductance, pinchoff voltage, and knee voltage are 0.65 µm, 0.11 A/cm, 200 mS/cm, 5.6 mS/cm, -1 V, and 0.65 V, respectively. Time-dependent two-dimensional simulation methods based on realistic models for doping profiles, high field transport, and interfaces have been used for analysis. The sensitivity of the device characteristics has also been simulated. Simulated results are in excellent agreement with measured data.

Electron-beam fabricated high-speed digital GaAs integrated circuits

The fabrication and performance of high-speed GaAs logic circuits incorporating submicrometer gate length FET's fabricated by electron-beam lithography are discussed. The process technology required for realizing 0.5-µm gate length devices is detailed. High-speed results including a 10-GHz logic gate, 34-ps gate delay for a ring oscillator, and a 4-GHz flip-flop are described.

A temperature model for the GaAs MESFET

This paper describes a new two-dimensional method for study of GaAs Schottky-barrier MESFET's. A modified form of the conduction current is used in which transport properties are described in terms of electron temperature rather than electric field. Nonequilibrium velocity effects such as velocity overshoot are included. Results for the one-dimensional GaAs diode and the two-dimensional GaAs MESFET are presented and compared to other studies that utilize the Monte Carlo procedure. Larger values of current cut-off frequency are predicted for submicrometer gate length MESFET's than in previous two-dimensional simulations which utilize the steady-state transport properties.

TA-A5 CMOS/SOS transistors with submicrometer gate lengths

TA-A5 CMOS/SOS transistors with submicrometer gate lengths

A study of high-speed normally off and normally on Al0.5Ga0.5As heterojunction gate GaAs FET's (HJFET)

The dc, small-signal microwave, and large-signal switching performance of normally off and normally on Al 0.5 Ga 0.5 As gate heterojunction GaAs field-effect transistors (HJFET) with submicrometer gate lengths are reported. The structure of both types of devices comprises an n-type 1017-cm-3Sn-doped active layer on a Cr-doped GaAs substrate, a p-type 1018-cm-3Ge-doped Al 0.5 Ga 0.5 As gate layer and a p+-type 5 × 1018-cm-3Ge-doped GaAs contact and cap layer on the top of the gate. The gate structure is obtained by selectively etching the p+-type GaAs and Al 0.5 Ga 0.5 As. Undercutting of the Al 0.5 Ga 0.5 As layer results in submicrometer gate lengths, and the resulting p+-GaAs overhang is used to self-align the source and the drain with respect to the gate. Normally off GaAs FET's with 0.5- to 0.7-µm long heterojunction gates exhibit maximum available power gains (MAG) of about 9 dB at 2 GHz. Large-signal pulse measurements indicate an intrinsic propagation delay of 40 ps with an arbitrarily chosen 100-Ω drain load resistance in a 50-Ω microstrip circuit. Normally on FET's with submicrometer gate lengths (∼0.6 µm) having a total gate periphery of 300 µm and a corresponding dc transconductance of 20-30 mmhos exhibit a MAG of 9.5 dB at 8 GHz. The internal propagation delay time measured under the same conditions as above is about 20 ps.

Submicrometer Self-Aligued GaAs MESFET (Short Papers)

This short paper presents a self-aligned technique which permits the production of submicrometer gate lengths and spacings between contacts. The exclusive use of standard photolithographic techniques makes this method interesting. Microwave measurements are reported for such a device with a 0.7-mu m gate length in a 2.2-mu m drain-source spacing. The yield of the process is usually better than 80 percent.