Abstract
A fully-scaled NMOS process was developed for VLSI cirsuits. Device isolation was achieved by channel stop implant using a reverse tone resist technique. This isolation process gives high field turn-on voltage, minimal narrow width effect and low body effect. A tri-level photoresist process was developed for gate definition. This process technology was demonstrated through the successful fabrication of an 8×8 bit parallel multiplier with submicrometer gatelengths. This 8×8 bit multiplier has a multiplication time of 9.5 ns.
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