Submicrometer Gate Lengths Research Articles

Deep‐Submicrometer Complementary Metal‐Oxide‐Semiconductor Transistors Based on Carbon Nanotube Films

AbstractSemiconducting carbon nanotube (CNT) films are considered promising channel materials for constructing complementary metal‐oxide semiconducting (CMOS) field‐effect transistors (FETs) for future high‐performance integrated circuits (ICs). However, the poor performance of short channel n‐type FETs built on solution‐derived CNT films hinders the development of truly symmetric CMOS FETs, especially as the gate length scales down to the submicrometer region. The performance of short channel n‐type FETs is improved here by using scandium contacts accompanied by a doping channel and high‐performance and symmetrical CMOS FETs with a deep submicrometer gate length are fabricated for the first time. The n‐type and p‐type CNT FETs with a 150 nm gate length exhibit a maximum on‐state currentIonof ≈270 µA µm−1and a peak transconductancegmof over 100 µS µm−1, representing the best CNT CMOS FETs thus far. Digital circuit and system benchmarking with the Intel circuit model indicates that the deep‐submicrometer CNT CMOS FETs show great advantages over the previously reported CMOS ICs based on CNT FETs or other semiconducting film‐based FETs.

Effects of Self-Heating on ${f}_{\text{T}}$ and ${f}_{\text{max}}$ Performance of Graphene Field-Effect Transistors

It has been shown that there can be a significant temperature increase in graphene field-effect transistors (GFETs) operating under high drain bias, which is required for power gain. However, the possible effects of self-heating on the high-frequency performance of GFETs have been weakly addressed so far. In this article, we report on an experimental and theoretical study of the effects of self-heating on dc and high-frequency performance of GFETs by introducing a method that allows accurate evaluation of the effective channel temperature of GFETs with a submicrometer gate length. In the method, theoretical expressions for the transit frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) and the maximum frequency of oscillation (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) based on the small-signal equivalent circuit parameters are used in combination with the models of the field- and temperature-dependent charge carrier concentration, velocity, and saturation velocity of GFETs. The thermal resistances found by our method are in good agreement with those obtained by the solution of the Laplace equation and by the method of thermo-sensitive electrical parameters. Our experiments and modeling indicate that the self-heating can significantly degrade the f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of GFETs at power densities above 1 mW/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , from approximately 25 to 20 GHz. This article provides valuable insights for further development of GFETs, taking into account the self-heating effects on the high-frequency performance.

Relaxation Processes in Submicron Heterotransistors with a System of Quantum Wells

The analysis of relaxation processes in submicrometer heterostructure transistors with the system of quantum walls is investigated. The methods of nano heterostructure design are developed including quantum effects and specific for ternary alloys scattering mechanism. Modeling based on the relaxation equations system for submicrometer heterostructures with quantum walls is fulfilled.The optical, acoustic, intervalley and doping scattering mechanisms is considered. New approach allows to study the influence of alloy scattering as well as. The relaxation times are expected for scattering mechanisms and the influence on field-speed and output characteristics of submicrometer heterostructure transistor are estimated.The modeling results take into account influence of casual fluctuations of the molar concentration of aluminium in the structure of transistor. The analysis of the scattering mechanisms is considered in the 2D-model of structure, that allows to estimate influence of the separate scattering mechanisms on the electronic gas in heterostructures with the systems of quantum walls. Polar optical phonons scattering is basic in such structures, while in an area gate-drain does not begin to prevail the intervalley scattering mechanism.It is shown that the average drift speed in the heterotransistor with two channel structure are more high, than in heterotransistor with one potential wall and two heterojunctions transistors have higher values of output current.The growth of the average drift speed in a structure with two quantum walls in comparison from heterotransistor with one quantum walls makes to 30-40%. It is related to the redistribution of electrons between potential walls with the loss of the energy at overcoming of barriers.The modeling results shown that warming-up of electronic gas and growth of the electrons temperature is a greater degree related to the electrons which drift in potential walls at heterojunctions.It is also necessary to take into account the dimensional quantization effect. This effect in heterostructure is require the calculation of discrete energy levels in quantum walls.Diminishing of the influence of strong electric-field effects in a two channel structure is related to the diminishing of scattering probability both on polar optical phonons and as a result of the injecting of electrons to lower heterojunction with high initial speed and small values of energy which diminishes also probability of the intervalley scattering.The model of calculation of the quantum walls influence on the longitudinal transport in the heterojunction transistors with submicrometer gate length are developed. The mathematical model can be used for the calculation of not only heterostructures transistor but also other constructions of multi-layered devices with the systems of quantum walls in the conditions of the strong electric fields.Ref. 13, fig. 19.

High Efficiency AlN/GaN HEMTs for Q-Band Applications with an Improved Thermal Dissipation

In this paper, we demonstrate Q-band power performance of carbon doped AlN/GaN high electron mobility transistors (HEMTs) using a deep sub-micrometer gate length (120 nm). With a maximum drain current density ID of 1.5 A/mm associated to a high electron confinement and an extrinsic transconductance gm of 500 mS/mm, this structure shows excellent electrical characteristics. A maximum oscillation frequency fmax of 242 GHz has been observed. As a result, a state-of-the-art combination at 40 GHz of output power density (POUT = 7 W/mm) and power added efficiency (PAE) of 52% up to VDS = 25V has been obtained. The achievement of such outstanding performance is attributed to the reduced thermal resistance (RTH) as compared to the commonly used double heterostructure by means of Raman thermography.

Suppression of Short-channel Effects by Double-gate Double-channel Device Design in Normally-off AlGaN/GaN MIS-HEMTs

ABSTRACT In this work, we have performed numerical simulations of normally-off AlGaN/GaN recessed Metal–Insulator-Semiconductor or MIS-HEMTs. A double-gate double-channel device design is proposed and analyzed using calibrated TCAD models. The dual-gate geometry is shown to provide an enhanced gate control over the double-channel, thereby suppressing the short-channel effects. The proposed device exhibits 72-mV/decade subthreshold slope, which is 50% improvement compared to the single-gate single-channel device with 3 µm gate length. Both the double-gate double-channel and single-gate single-channel structures are compared for their ability to counter short-channel effects in aggressively scaled MIS-HEMT devices. It is shown that, double-gate design is superior to single-gate single-channel device with 80% improvement in drain-induced barrier lowering at sub-micrometer gate lengths.

High power, high PAE Q-band sub-10 nm barrier thickness AlN/GaN HEMTs

We report a state-of-the-art performance of deep sub-micrometer gate length AlN/GaN High Electron Mobility Transistors using a thick in situ SiN cap layer. With 120 nm gate length large-signal load-pull measurements showed a peak power-added-efficiency (PAE) above 45%. To the best of our knowledge, this represents the highest PAE for GaN HEMTs at 40 GHz, especially when using a sub-10 nm barrier thickness. Furthermore, state-of-the-art peak output power density above 6 W mm−1 at 40 GHz has been achieved in pulsed mode. This is the highest output power ever reported for sub-10 nm barrier thickness Q-Band GaN devices. The performance improvement is attributed to the thick in situ SiN cap layer and optimized electron confinement allowing higher voltage operation and lower dispersion under high electric field.

High Electron Velocity Submicrometer AlN/GaN MOS-HEMTs on Freestanding GaN Substrates

AlN/GaN heterostructures with 1700-cm2/V·s Hall mobility have been grown by molecular beam epitaxy on freestanding GaN substrates. Submicrometer gate-length (LG) metal-oxide-semiconductor (MOS) high-electron-mobility transistors (HEMTs) fabricated from this material show excellent dc and RF performance. LG = 100 nm devices exhibited a drain current density of 1.5 A/mm, current gain cutoff frequency fT of 165 GHz, a maximum frequency of oscillation fmax of 171 GHz, and intrinsic average electron velocity ve of 1.5 ×107 cm/s. The 40-GHz load-pull measurements of LG = 140 nm devices showed 1-W/mm output power, with a 4.6-dB gain and 17% power-added efficiency. GaN substrates provide a way of achieving high mobility, high ve, and high RF performance in AlN/GaN transistors.

12 GHz $F_{\rm MAX}$GaN/AlN/AlGaN Nanowire MISFET

GaN/AlN/AlGaN/GaN nanowire metal-insulator-semiconductor field-effect transistors (MISFETs) have been fabricated for the first time with submicrometer gate lengths. Their microwave performances were investigated. An intrinsic current-gain cutoff frequency ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of 5 GHz as well as an intrinsic maximum available gain ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</sub> ) cutoff frequency of 12 GHz have been obtained for the first time and associated with a gate length of 0.5 mum. These results show the great potentiality of GaN-based nanowire FETs for microwave applications.

T-gate geometric (solution for submicrometer gate length) HEMT: Physical analysis, modeling and implementation as parasitic elements and its usage as dual gate for variable gain amplifiers

In order to achieve superior RF performance, short gate length is required for the compound semiconductor field effect transistors, but the limitation in lithography for submicrometer gate lengths leads to the formation of various metal–insulator geometries like T-gate [Sandeep R. Bahl, Jesus A. del Alamo, Physics of breakdown in InAlAs/ n +-InGaAs heterostructure field-effect transistors, IEEE Trans. Electron Devices 41 (12) (1994) 2268–2275]. These geometries are the combination of various Metal-Semiconductor (MS)/Metal–Air-Semiconductor (MAS) contacts. Moreover, field plates [S. Karmalkar, M.S. Shur, G. Simin, M. Asif Khan, Field-plate engineering for HFETs, IEEE Trans. Electron Devices 52 (2005) 2534–2540] are also being fabricated these days, mainly at the drain end ( Γ -gate) having Metal–Insulator-Semiconductor (MIS) instead of MAS contact with the intention of increasing the breakdown voltage of the device. To realize the effect of upper gate electrode in the T-gate structure and field plates, an analytical model has been proposed in the present article by dividing the whole structure into MS/MIS contact regions, applying current continuity among them and solving iteratively. The model proposed for Metal–Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) [R. Gupta, S.K. Aggarwal, M. Gupta, R.S. Gupta, Analytical model for metal insulator semiconductor high electron mobility transistor (MISHEMT) for its high frequency and high power applications, J. Semicond. Technol. Sci. 6 (3) (2006) 189–198], is equally applicable to High Electron Mobility Transistors (HEMT) and has been used to formulate this model. In this paper, various structures and geometries have been compared to anticipate the need of T-gate modeling. The effect of MIS contacts has been implemented as parasitic resistance and capacitance and has also been studied to control the middle conventional gate as in dual gate technology by applying separate voltages across it. The results obtained using the proposed analytical scheme has been compared with simulated and experimental results, to prove the validity of our model.

MESFETs on H-terminated Single Crystal Diamond

AbstractEpitaxial diamond films were deposited on polished single crystal Ib type HPHT diamond plates of (100) orientation by microwave CVD. The epilayers were used for the fabrication of surface channel MESFET structures having sub-micrometer gate length in the range 200-800 nm. Realized devices show maximum drain current and trasconductance values of about 190 mA/mm and 80 mS/mm, respectively, for MESFETs having 200 nm gate length. RF performance evaluation gave cut off frequency of about 14 GHz and maximum oscillation frequency of more than 26 GHz for the same device geometry.

A Correlated Diffusion Noise Model for the Field-Effect Transistor

A numerical approach to simulate the intrinsic noise sources within transistors is described, and the impact of spatial correlation between local fluctuations is investigated. Using a 2-D numerical device solver, spectral densities for the gate and drain noise current sources and their correlation are evaluated using a Green's function approach, which is an equivalent of Shockley's impedance field method. Case studies with an AlGaN/GaN high electron mobility transistor are supported by measurement data. Using a spatial noise source correlation model, similar terminal noise is found to the case of an uncorrelated diffusion noise source. Therefore, using uncorrelated local noise sources to calculate the intrinsic terminal noise is found to be valid even for the submicrometer gate length field-effect transistor studied.

Characteristics of Aluminum Substitution Technology for Self-Aligned Full Metal Gate nMOSFETs

We investigated self-aligned metal gate MOSFETs that feature an ideal low-resistance aluminum gate using aluminum substitution technology (AST). This technology can be used to fabricate metal gate MOSFETs with submicrometer gate lengths and 1.8-nm-thick gate insulators processed at 350/spl deg/C. We found that AST is especially suitable for MOSFET with short gate lengths, because the aluminum substitution is accelerated under gate lengths of 0.1-/spl mu/m. We will explain the aluminum substitution phenomenon based on the counter diffusion between aluminum and silicon and the capillary effect. We will also show the electric properties of full metal gate nMOSFET produced using AST with a 60-nm gate length.

Energy model for optically controlled MESFETs

An energy-based transport model for the analysis of illuminated microwave active devices is presented. The model is based on the Boltzmann's transport equation, with optical carrier generation and carrier recombination accounted for. The simulation results are compared with the conventional local-field mobility models based on drift-diffusion formulations. It is shown that the drift-diffusion models lose their applicability in submicrometer gate-length devices. The presented time-domain model has a great potential in the analysis of microwave devices under ac and pulsed illumination conditions.

Energy model for optically controlled MESFETs

An energy-based transport model for the analysis of illuminated microwave active devices is presented. The model is based on the Boltzmann's transport equation, with optical carrier generation and carrier recombination accounted for. The simulation results are compared with the conventional local-field mobility models based on drift-diffusion formulations. It is shown that the drift-diffusion models lose their applicability in submicrometer gate-length devices. The presented time-domain model has a great potential in the analysis of microwave devices under ac and pulsed illumination conditions. © 2000 John Wiley & Sons, Inc. Microwave Opt Technol Lett 26: 48–52, 2000.

Design Aspects of a Submicrometer Gate Length High Electron Mobility Transistor

An optimized model based on the solution of two-dimensional Poissons equation with improved performance for design aspect of a submicron gate length device is proposed. It analyses the dependence of threshold voltage on the process parameters and gives an idea about the choice of the doping concentration and AIGaAs layer thickness to obtain a minimum threshold voltage variation. The model discusses the different short channel parameters with their effect on the subthreshold current. When calculated results from the present model are compared with available experimental aata, a close agreement between the two is observed, thereby, confirming the validity of the model.

Characteristics of deep-submicrometer MOSFET and its empirical nonlinear RF model

Si MOSFET's with submicrometer gate length were fabricated and characterized by RF evaluation. Devices with a 0.25 /spl mu/m gate length demonstrated a g/sub m/ of 258 mS/mm, an f/sub T/ of 28 GHz, and a minimum noise figure of 1.8 dB at 900 MHz. A nonlinear device model was constructed based on the measured results. Empirical equations are used to represent the nonlinear elements such as g/sub m/, C/sub gs/, C/sub gd/, C/sub ds/, and R/sub out/. These nonlinear elements, together with device parasitics, provide designers with a comprehensive model for using these devices for RF circuits.

Analytical noise model with the influence of shot noise induced by the gate leakage current for submicrometer gate-length high-electron-mobility transistors

A new high-frequency noise model which takes into account the influence of shot noise induced by the gate leakage current is introduced; the model accurately explains the observed minimum noise figure of submicrometer gate-length HEMT's as a function of frequency. Based on the steady-state Nyquist theorem for multiterminal devices recently reported, the minimum noise figure and the corresponding optimum source impedance of the microwave field effect transistors are expressed as functions of the measurable device parameters including noise spectral intensities and small-signal circuit parameters. The derived minimum noise figure can be shown to reduce to a simple form, i.e., an empirical relation with two fitting constant. The simple form and the derived formulas for the optimum source impedance can explain very well the experimental findings of the submicrometer gate-length high electron mobility transistors over the extended microwave frequency range and also provide the informations needed for the design of microwave low noise amplifiers.

High-performance submicrometer gatelength GaInAs/InP composite channel HEMT's with regrown ohmic contacts

This letter reports DC and RF performance of 0.25 /spl mu/m gatelength GaInAs/InP composite channel HEMT's with nonalloyed, regrown ohmic contacts by MOCVD. Regrown channel contacts are used to achieve low contact resistance (0.35 /spl Omega/-mm) to (50 /spl Aring/) GaInAs/(150 /spl Aring/) InP composite channel HEMT's. High transconductance (600 mS/mm), high full channel current (650 mA/mm), and high peak cut-off frequencies (F/sub t/=70 GHz, F/sub max/=170 GHz) are observed. Contact transfer resistance of regrown channel contacts is compared to conventional alloyed contacts for varying GaInAs/InP channel composition.

Study of hot electron degradation in submicrometer gate length MOS transistor fabricated with selectively doped substrate engineering

Investigations are made on the performance and hot electron degradation of sub-μm MOS transistors fabricated with an improved selectively doped substrate (SDS) and with the conventional deep punch through implant (DPI) structures. The sub-μm gate length of the transistor was defined by a novel subtractive photolithography technique. The technique is described and the process details are given. The sub-μm transistor performance is characterised by electron mobility, inverse subthreshold slope, substrate sensitivity and drain induced barrier lowering (DIBL) for the two structures. The substrate current and hot electron degradation effect (HED) were measured and the results are compared for SDS and DPI techniques. It is shown that SDS structure reduces HED and surface punchthrough effects in sub-μm MOS transistors.

An excimer-laser-based nanosecond thermal diffusion technique for ultra-shallow pn junction fabrication

Abstract In this paper we review the development of nanosecond thermal diffusion (NTD), a new doping technology which utilizes excimer-laser-induced heating to incorporate and diffuse impurities in silicon wafers. With thermal anneals less than 200 ns in duration, the new laser-based method permits simple, low-temperature fabrication of the ultrashallow p-n junctions necessary for deep-submicrometer MOS and bipolar transistors. In a multifaceted research effort, we are building advanced equipment, developing accurate simulation tools, and designing effective process flows to demonstrate the viability of the NTD technique for manufacturing applications. To date we have fabricated p+-n and n+-p diodes with 300 A junction depth, submicrometer PMOS transistors, and narrow-base regions in bipolar devices. Included in our results are: ultra-shallow diodes with ideality factors of 1.01–1.10 over seven decades of current, reverse leakage currents less than 10 nA/cm2 at 5 V reverse bias, and breakdown voltages in excess of 100 V, MOS devices that demonstrate excellent short channel behavior and no threshold voltage shift at submicrometer gate lengths, and bipolar transistors that incorporate base widths which range from 700 A to 1200 A and exhibit current gains between 50 and 200.