Effects of Self-Heating on ${f}_{\text{T}}$ and ${f}_{\text{max}}$ Performance of Graphene Field-Effect Transistors

Marlene Bonmann,Xinxin Yang,Martin Otto,Luca Banszerus,Marijana Krivic,Jan Stake,Daniel Neumaier,Christoph Stampfer,Andrei Vorobiev

doi:10.1109/ted.2020.2965004

Abstract

It has been shown that there can be a significant temperature increase in graphene field-effect transistors (GFETs) operating under high drain bias, which is required for power gain. However, the possible effects of self-heating on the high-frequency performance of GFETs have been weakly addressed so far. In this article, we report on an experimental and theoretical study of the effects of self-heating on dc and high-frequency performance of GFETs by introducing a method that allows accurate evaluation of the effective channel temperature of GFETs with a submicrometer gate length. In the method, theoretical expressions for the transit frequency (f T ) and the maximum frequency of oscillation (f max ) based on the small-signal equivalent circuit parameters are used in combination with the models of the field- and temperature-dependent charge carrier concentration, velocity, and saturation velocity of GFETs. The thermal resistances found by our method are in good agreement with those obtained by the solution of the Laplace equation and by the method of thermo-sensitive electrical parameters. Our experiments and modeling indicate that the self-heating can significantly degrade the f T and f max of GFETs at power densities above 1 mW/μm 2 , from approximately 25 to 20 GHz. This article provides valuable insights for further development of GFETs, taking into account the self-heating effects on the high-frequency performance.

Highlights

T HE implementation of the fairly new class of 2-D materials, such as graphene [1] and MoS2 [2], opens up opportunities for new device concepts within electronics and Manuscript received August 26, 2019; revised October 23, 2019 and December 2, 2019; accepted January 3, 2020
Detrapping is a thermally activated process leading to the release of more electrons from traps with increasing temperature supported by the negative bias at the gate
We presented a new method that allows for the evaluation of the thermal resistance of graphene field-effect transistors (GFETs) with a submicrometer gate length

Summary

Introduction

T HE implementation of the fairly new class of 2-D materials, such as graphene [1] and MoS2 [2], opens up opportunities for new device concepts within electronics and Manuscript received August 26, 2019; revised October 23, 2019 and December 2, 2019; accepted January 3, 2020. Date of publication January 29, 2020; date of current version February 26, 2020. Luca Banszerus and Christoph Stampfer are with the 2nd Institute of Physics, RWTH Aachen University, 52074 Aachen, Germany. Martin Otto and Daniel Neumaier are with the Advanced Microelectronic Center Aachen, AMO GmbH, 52074 Aachen, Germany

Methods

Results

Conclusion