Study of hot electron degradation in submicrometer gate length MOS transistor fabricated with selectively doped substrate engineering

Abstract

Investigations are made on the performance and hot electron degradation of sub-μm MOS transistors fabricated with an improved selectively doped substrate (SDS) and with the conventional deep punch through implant (DPI) structures. The sub-μm gate length of the transistor was defined by a novel subtractive photolithography technique. The technique is described and the process details are given. The sub-μm transistor performance is characterised by electron mobility, inverse subthreshold slope, substrate sensitivity and drain induced barrier lowering (DIBL) for the two structures. The substrate current and hot electron degradation effect (HED) were measured and the results are compared for SDS and DPI techniques. It is shown that SDS structure reduces HED and surface punchthrough effects in sub-μm MOS transistors.