Stress-induced Voiding Research Articles

Cu配線の信頼性と界面： EM，SIV，TDDBにおける界面の寄与と制御

The contributions of the “interface” on interconnect reliability are investigated in some previous work. For electromigration and stress-induced voiding, Cu/dielectrics interface has a key role as a dominant diffusion path of Cu. A surface treatment after chemical mechanical polishing affects lifetime distribution of time-dependent dielectric breakdown. The defect density on the interface is a key factor to control the early failure. In this paper, some advanced metallization process and its effects to suppress the reliability issues are introduced. To adapt the novel process technologies successfully in product line, these results will provide valuable information.

Suppression of Stress-Induced Voiding by Controlling Microstructure of Cu Electroplated Films

In advanced LSI devices, the filling capability for the electroplating (ECP) process, impurities in Cu film, and grain growth after ECP are important properties of Cu interconnect reliability. It has been reported that the Cu grain growth depends on the ECP-Cu film characteristics and the annealing conditions. In this study, we focus on the deposition thickness of ECP-Cu films to control their microstructure. It is revealed that a thicker ECP-Cu film enlarges the Cu grain size and reduces the number of small grains. It is also revealed that Cu grains in a wide line with a thicker ECP-Cu film are larger, leading to reliability improvement. A film with larger grains has fewer grain boundaries and fewer diffusion paths of vacancies, and a film with fewer small grains has a decreased number of vacancies. As a result, stress-induced voiding phenomena are apparently suppressed by increasing the thickness of deposited ECP-Cu film.

Lifetime Distribution Analysis of Stress-Induced Voiding Based on Void Nucleation and Growth in Cu/Low-$\kappa$ Interconnects

The lifetime distribution of stress-induced voiding with area scaling is investigated on a void nucleation and growth framework. The distribution resulting from the convolution integrals of the time to void nucleation and the time for void growth was applied to observed data. The time to void nucleation showed non-Poisson area scaling, whereas the time for void growth showed Poisson area scaling. Therefore, the area scaling effects were applied to a negative binominal distribution and a Poisson distribution, respectively. With a Monte Carlo simulation, it was found that the time for void growth will be dominant for the product-level lifetime.

Stress-induced voiding in nickel silicide

We have discovered stress-induced voiding in a Ni-Pt silicide line fabricated on a 45-nm-node logic device. The voiding led to the disconnection of a narrow silicide line between gates in a wide active area. In the device pattern, the silicide was strained by a shallow trench isolation structure because the filled film in the structure anisotropically loaded tensile stress into the active line under the silicide between the gates. The voids were detected as a failure by thoroughly probing the silicide resistance; the incidence of voids was at the six-sigma confidence level. The voids occurred in the silicide line, which contained di-metal silicide even after a second silicidation annealing. They were suppressed by the formation of monosilicide in the silicide line during a second silicidation annealing. This is attributed to the Ni migration accompanying the counter flow of vacancies being suppressed in the monosilicide under the interconnect fabrication thermal budget. As a result, the defect density for 8-Mbit static random access memory fabricated in 45-nm technology was reduced by about half.

Distinguishing between Individual Contributions to the Via Resistance in Carbon Nanotubes Based Interconnects

We report on the design and fabrication of carbon nanotube (CNT) vias based on a hybrid metal/CNT technology. The CNTs were integrated on a 4 inch Si wafer platform using conventional semiconductor processes. Multiwalled carbon nanotubes were grown vertically aligned on a copper based metal line. Via holes were prepared using a single damascene process. By employing a substrate-based selective deactivation of the catalyst, CNT growth was restricted to the vias. Following this process scheme, the impact of post-CNT growth procedures, like chemical mechanical planarization and sample annealing, were investigated and electrically evaluated using conductive atomic force microscopy and current-voltage (I-V) characterization. Probing 440 individual structures, the resistance of two series-connected 5 μm vias were determined to be (800 ± 60) Ω after chemical mechanical planarization. By obtaining the I-V characteristics of single CNTs within an individual via, we found that the measured resistance is determined by the contact resistance of the CNT-metal interface. Two mechanisms were found to be relevant here. First partial oxidation of the metal interface during processing, and secondly, stress-induced voiding caused by the high temperatures during the CNT growth process. Changes in the integration scheme to reduce the overall CNT via resistance are proposed.

Applications of finite element methods for reliability study of ULSI interconnections

Three main failure mechanisms of ULSI interconnects are the electromigration (EM), stress induced voiding (SIV) and low-k dielectric breakdown. Reliability tests for these mechanisms are too long to meet the development time requirement, and the underlying dominant mechanisms cannot be identified, rendering difficulty in design-in reliability for integrated circuit. Facing the challenges in the reliability study of the interconnect system, physics based simulation and modeling is found to be essential, and finite element method (FEM) is a suitable tool. A few examples on the application of FEM to study the degradation processes and identification of potential failure sites in interconnects due to EM and SIV are given here. The study of the process induced degradation of the effective k value of low-k dielectric in ULSI interconnect system using FEM is also presented.

Stress migration model for Cu interconnect reliability analysis

Stress migration (SM) reliability data have been treated qualitatively to define pass or fail criteria in the past. However, realistic quantitative SM analysis and lifetime estimates for products were not available due to lack of a suitable SM model. In this paper, we establish a comprehensive SM model for quantitative stress-induced-voiding (SIV) risk analysis for 32 nm technology and beyond. It was found that the SIV risk is dependent on both stress temperatures and geometric structural line widths as driving forces. Based on the new SM model, the SM lifetime can be estimated from measurable SM data and accelerated SM test methods can be designed to meet the qualification criteria.

Nonlinear oxidation kinetics of nickel cermets

The oxidation of a cermet of screen-printed nickel (Ni) and gadolinia-doped ceria (CGO) with an approximate median porosity of 50vol.% has been studied via in situ X-ray diffraction and focused ion beam nanotomography in the temperature range 773–848K. The oxidation kinetics of Ni to NiO is found to be highly nonlinear with an apparent activation energy of 2.8(2)eV in this temperature range. The nonlinear oxidation kinetics found is in good agreement with theoretical works on oxide growth driven by nonlinear inbuilt fields. Stress-induced Kirkendall void formation has been identified as the physical process that enhances the oxidation of Ni/CGO cermets. Compressive stresses within the Ni matrix result from the thermal expansion mismatch of Ni and CGO and cause plastic deformation as they exceed the yield stress of the Ni matrix. The pore size distribution of Kirkendall voids formed has been measured by FIB nanotomography and shows a significant temperature dependence. It is shown that even one cycle of reoxidation changes irreversibly the microstructure of the cermet which can be interpreted as the onset and main contribution to the mechanical degradation of the cermet.

Prediction of Stress Induced Voiding Reliability in Cu Damascene Interconnect by Computer Aided Vacancy Migration Analysis

The method of computer aided vacancy migration analysis has been developed to predict the stress induced voiding (SiV) reliability. In this method, distribution of hydrostatic stress was calculated by the finite element analysis (FEA), and vacancy concentration distribution was calculated by the finite difference analysis (FDA). In this paper, SiV acceleration tests were conducted in various widths of Cu lines in organic ultralow-k dielectric (Cu/Ta/ULK/SiCN) or silicon oxide dielectric (Cu/Ta/SiO2/SiCN) and these results were compared with the results of the vacancy migration analyses. The number of SiV failures increased in the line with width of 0.35 µm for Cu/Ta/SiO2/SiCN interconnects and 0.20 µm for Cu/Ta/ULK/SiCN interconnects, respectively, under SiV acceleration tests. The results obtained by vacancy migration analysis show similar behavior as the results of SiV acceleration tests. These results reveal that the vacancy migration analysis is useful to predict reliability of interconnects.

Finite element simulation of hydrostatic stress in copper interconnects

This work focuses on numerical modeling of hydrostatic stress, which is critical to the formation of stress-induced voiding (SIV) in copper damascene interconnects. Using three-dimensional finite element analysis, the distribution of hydrostatic stress is examined in copper interconnects and models are based on the samples, which are fabricated in industry. In addition, hydrostatic stress is studied through the influences of different low-k dielectrics, barrier layers and line widths of copper lines, and the results indicate that hydrostatic stress is strongly dependent on these factors. Hydrostatic stress is highly non-uniform throughout the copper structure and the highest tensile hydrostatic stress exists on the top interface of all the copper lines.

3D-interconnect: Visualization of extrusion and voids induced in copper-filled through-silicon vias (TSVs) at various temperatures using X-ray microscopy

Visualization of voids and copper extrusion in copper-filled through-silicon vias (TSVs) under different annealing conditions is greatly enhanced using X-ray microscopy. In addition, the dimensions of the TSVs after Cu deposition can also be measured by 3D reconstruction. Surface inspection found mushroom defects on the top of TSVs after deposition of the etch stop layer, forming a small bump on top of the TSV. The ~50nm etch stop layer is part of the dielectric stack used before metal 1 is deposited on top of the TSVs. The TSVs are annealed, then undergo chemical mechanical polishing (CMP) before the etch stop layer is deposited at 350^oC. It is assumed that after CMP the etch stop layer on top of the TSVs is planar. However, cross-sectional scanning electron microscopy (XSEM) shows mushroom defects but no particles at the interface of the TSV and the etch stop layer. This study investigates the changes in copper extrusion and induced voiding that result from different annealing temperatures. Round TSVs [email protected] deep and [email protected] in diameter were filled with copper by electrochemical deposition (ECD), followed by chemical mechanical polishing and pre-annealing to 150^oC for one hour. Based upon the material properties of TSVs, the high density copper absorbs photon energy more strongly than silicon or air. This results in good contrast within the copper-filled vias when X-ray micrographs are taken and allows voids within the material to be seen. A lab-based X-ray microscope with 8Kev X-ray energy allows a penetration of [email protected] into the silicon. Consequently, sample preparation requires wafers to be backside polished from an initial thickness of [email protected] to <[email protected] When scanned with a lab-based X-ray microscope, a set of TSVs is imaged and the 3D X-ray tomography shows voids or seamlines at the bottom of the TSVs. This sample was annealed to 225^oC and 300^oC, respectively. Upon scanning the same TSVs, the X-ray micrograph shows the seamline changes shape, voids are induced at the center of TSVs, and copper extrudes on top of the TSVs. This suggests the copper extrusion causes the etch stop layer to form a defect at the top of the TSVs. An X-ray microscope offers the potential to inspect voids in multiple vias at the same time without a physical cross section of the TSVs. This technique can be used to advance the study of different stress-induced voids used for 3D interconnects.

Growth Mechanism and Prevention Measure of Stress-Induced Voids in Copper Interconnects

Growth Mechanism and Prevention Measure of Stress-Induced Voids in Copper Interconnects

Characterization of a controlled electroless deposition of copper thin film on germanium and silicon surfaces

Nanofilms of copper were deposited on silicon and, for the first time, on polycrystalline germanium substrates by electroless deposition. Germanium or silicon disks were immersed in a 10mM copper sulfate solution containing dilute hydrofluoric acid at room temperature. This simple one-step deposition does not require the use of laborious operations or expensive equipment, that the reaction medium be degassed, or that the film be annealed. The copper film grows in a few minutes, producing a film on both Ge and Si that covers a very large area of the substrate in contrast to other metals such as Au, Ag, Pt and Pd for which deposition on Ge and Si produces islands or dendrites. Atomic force microscopy, X-ray photoelectron spectroscopy (XPS) and powder X-ray diffraction (PXRD) were used to characterize the microstructure and confirmed the formation of elemental copper nanofilms. The AFM micrographs reveal a Stranski–Krastanov type of film growth (layers+islands) that varies with the length of time the Ge or Si substrate is immersed in the CuSO4 solution. Thicker films were observed on the Ge than on the Si substrate resulting in larger particles and rougher surface than on Si. XPS analysis shows that the elemental copper is deposited on both Ge and Si substrates and that the films oxidize over a period of weeks with air exposure at room temperature. Finally, PXRD data reveal two preferential orientations (111) and (200) for the copper crystallites grown on both Ge and Si. The same intensity of the (111)-texture was measured on both Ge and Si substrate which is an important result because it has been shown that the (111) texture reduces stress-induced voiding and increases resistance to electromigration in metal interconnects.

Void Growth Behavior in ULSI Cu Interconnections by Grain-Boundary Diffusion Simulation

The behavior of void growth in ultra-large-scale integration Cu interconnections has been investigated by grain-boundary diffusion simulation to confirm the effectiveness of the high-pressure reflow process for suppressing stress-induced voiding. Void growth was simulated by combining stress analysis and atomic flux analysis. The former was calculated by the finite-element method (FEM), and the latter was calculated by an unusual FEM in which grain boundaries were defined as elements. From the results of void growth analysis, we found that voids tend to disappear during the isochronal annealing step and that the void shrinkage rate can be increased by two to three times by applying pressure of 150 MPa compared with normal-pressure annealing. From the simulation results, it can be conjectured that the high-pressure reflow process is effective for eliminating voids in via holes of Cu interconnections.

Interconnect reliability – A study of the effect of dimensional and porosity scaling

A number of challenges linked to the reliability characterization of downscaled back-end-of-line copper/low- k interconnects are covered. Concerning copper reliability, it is shown using early data on 30 nm ½pitch that advanced barrier/seed/plating options can counteract models that predict decreased electromigration performance in smaller dimensions. Regarding stress-induced voiding, it is discussed that porosity scaling negatively influences metal degradation due to increased stress gradients. Also, since copper degradation during high temperature storage tests is driven by different failure mechanisms, it is argued that tests at a wide range of temperatures are needed to characterize stress-induced voiding in copper/low- k systems at normal operating conditions. In addition, it is suggested that the current knowledge on the dependence of interconnect pitches and dielectric porosity on stress in copper lines needs to be taken into account when building finite element models of copper/low- k stacks. This is motivated by highlighting results of our recent study where the copper strain is varied for different copper dimensions and pattern densities. Finally, because the reliability margin of time dependent dielectric breakdown of scaled intermetal dielectrics becomes smaller, it is put forward that understanding the low voltage behaviour of time dependent dielectric breakdown becomes indispensable. A case study using fully passivated MOS capacitors without metallic barrier between the copper and the dielectric is detailed out and differences in current versus time behaviour and distributional shapes between low and high fields are highlighted.

Texture and stress analysis of 120 nm copper interconnects

A scanning transmission electron microscope diffraction technique was used to determine the local orientation of copper grains in 120 nm copper interconnect (CI) lines. These grains exhibit a normal orientation while the and the type orientations are present along the length and width of the CI line, respectively. Stresses, as high as 625 MPa, are present at the copper/diffusion barrier triple junctions that in conjunction with large stress gradients may induce stress-induced void formation upon thermal cycling.

Scaling effects on microstructure and reliability for Cu interconnects

Abstract Continuous scaling of Cu interconnect structures can significantly impact reliability-limiting processes such as electromigration and stress-induced voiding. Prior to the 65 nm technology node, mass transport under electromigration is dominated by diffusion along the Cu/dielectric cap interface and the electromigration lifetime will degrade by about half for every generation, even with the same current density. Beyond the 65 nm node, small grains were found to mix with bamboo grains in the 90 nm Cu damascene lines and the contribution of the grain boundary transport degraded the electromigration lifetime. The scaling effects on microstructure and electromigration reliability are examined in this paper with the objective of identifying the key issues and exploring potential solutions for sub-100 nm Cu interconnects. We discuss first the scaling effect on electromigration lifetime and the effect due to the small grains on electromigration lifetime and statistics. This is followed by a discussion on grain growth studies focusing on the formation of small grains and a recent simulation study on small grain effect on electromigration reliability. This paper concludes with a discussion of some recent developments in analytical techniques to investigate grain structure and electromigration reliability in sub-100 nm Cu lines.

Structure-dependent behavior of stress-induced voiding in Cu interconnects

Stress modeling and cross-section failure analysis by focused-ion-beam have been used to investigate stress-induced voiding phenomena in Cu interconnects. The voiding mechanism and the effect of the interconnect structure on the stress migration have been studied. The results show that the most concentrated tensile stress appears and voids form at corners of vias on top surfaces of Cu M1 lines. A simple model of stress induced voiding in which vacancies arise due to the increase of the chemical potential under tensile stress and diffuse under the force of stress gradient along the main diffusing path indicates that stress gradient rather than stress itself determines the voiding rate. Cu interconnects with larger vias show less resistance to stress-induced voiding due to larger stress gradient at corners of vias.

Stress-induced phenomena in nanosized copper interconnect structures studied by x-ray and electron microscopy

We present the first dynamic study of damage mechanisms in nanosized on-chip Cu interconnects caused by stress-induced voiding in advanced integrated circuits. Synchrotron-based transmission x-ray microscopy is applied to visualize the void evolution and conical dark-field analysis in the transmission electron microscopy to characterize the Cu microstructure. Our x-ray microscopy measurements showed, in contradiction to electromigration studies, no void movement over large dimensions during the stress-induced void evolution. We observed in via/line Cu interconnect structures that voids are formed directly beneath the via, i.e., in the Cu wide line at the edge of the via bottom. It is concluded that voids are originally formed at the site where eventually the catastrophic failure occurs. During stress migration tests, Cu atoms migrate from regions of low stress to regions of high tensile stress, and simultaneously, vacancies migrate along the stress gradient (within a limited range of some microns) in the opposite direction to the location where small vias connect wide Cu lines. The stress distribution and the driving forces for atomic transport depend strongly on the particular geometry of the tested structure but also on interface bonding and metal microstructure. Vacancies form agglomerates and subsequently voids that grow further. The void growth rate depends on the Cu thin film material and its microstructure, particularly the grain size and the grain orientations. The Cu microstructure in the surroundings of the formed void shows that Cu grains are predominantly (111) oriented relatively to the wafer surface. Interfaces and grain boundaries, and particularly their orientation, determine the void evolution dynamics.

Multilevel Interconnect With Air-Gap Structure for Next-Generation Interconnections

A misalignment-free multilevel air-gap interconnect with a via-base structure was fabricated by self-aligned gap formation and etch back. Its reliability was investigated by measuring stress-induced voiding, electromigration (EM), and time-dependent dielectric breakdown (TDDB). There was no via degradation after thermal stress (at 200degC for 500 h). The EM lifetime was the same as that of a conventional damascene interconnect, and the TDDB lifetime was about two orders of magnitude longer. Increasing the etch-back thickness of the interlayer dielectric increased the capacitance reduction by about 17%-32%. The frequency of a ring oscillator with an air-gap interconnect was higher by 17% on average than that with a conventional damascene interconnect. The simulation results demonstrate that this air-gap interconnect has the effective dielectric constant required for next-generation interconnects (22-nm node).