Stress-induced Voiding Research Articles

Stress-induced and electromigration voiding in aluminum interconnects passivated with silicon nitride

Void nucleation in aluminum interconnects passivated with silicon nitride was studied using a high voltage scanning electron microscope. Extensive stress-induced voiding was observed in these interconnects independent of the passivation thickness. Some of the stress-induced and electromigration-induced voids formed away from the interconnect sidewall in contrast to results from other studies of void nucleation in passivated aluminum lines. Nuclear reaction analysis measured large amounts of hydrogen in the aluminum films passivated with silicon nitride. Transmission electron microscopy showed a high density of nanometer-sized bubbles in the aluminum. These bubbles, which are thought to have formed from hydrogen that evolved from the silicon nitride layer during processing, served as nucleation sites for stress- and electromigration-induced voids.

Stress-Induced Voiding in Sputtered TiSi[sub x] Complementary Metal Oxide Silicon Gate Electrodes

We examined the effect of shallow trench isolation (STI) process for the Si ultralarge-scaled integrated circuit on the thermal stability of the bar resistance and the internal void formation of sputtered-/poly-Si gate electrodes. Among the examined process variables, the STI step height can strongly affect the density of voids formed between the poly-Si and the films after the silicidation annealing. Above a STI step height of 400 Å, many clear voids were observed at the STI boundaries by scanning electron microscopy. The thermal stability of the sheet resistance for the /poly-Si gate electrode was investigated at various STI step heights and Si/Ti molar ratios (x) of the composite target. With the decrease in STI step height from 400 to 200 Å, the average at a 0.16 μm linewidth was enhanced from ∼60 to 15 Ω/□ after postannealing at 800°C for 2 h. With the increase of x from 2.1 to 2.3, the thermal stability of was also greatly enhanced showing an average of ∼15 Ω/□ at a 400 Å STI step height. From this study, we suggest that the stress-induced voiding at /poly-Si interface plays one of key roles in thermal degradation of due to the highly developed triaxial stress state in the gate electrode film. © 2002 The Electrochemical Society. All rights reserved.

Combined low-frequency noise and resistance measurements for void extraction in deep-submicrometer interconnects

Electromigration stress can give rise to voids that increase the resistance and localized thermal stress in interconnects. Estimation of the extent of voiding can provide information on the material quality and the amount of degradation that has resulted from the electrical stress. In this paper, a model is proposed that can be used to estimate the effective void volume in deep-submicrometer interconnects. The model uses a combination of low-frequency noise and resistance measurements, and also considers the thermal coefficient of resistance in calculating the change in resistance of the interconnect line. A deconvolution scheme was employed to extract the 1/f noise component from the noise-measurements to improve the accuracy of the extraction algorithm. To verify the accuracy of the model, the focused ion beam (FIB) technique was used to mill holes (to simulate voids) of known dimensions. The model was further applied to an electromigration stress study of aluminum (Al) interconnects as a method of testing its validity for stress-induced voids. The proposed technique is a useful reliability tool for void detection in deep-submicrometer interconnects.

Diffuse interface model for electromigration and stress voiding

We report a diffuse interface or phase field model for simulating electromigration and stress-induced void evolution in interconnect lines. Our approach is based on the introduction of an order parameter field to characterize the damaged state of the interconnect. The order parameter takes on distinct uniform values within the material and the void, varying rapidly from one to the other over narrow interfacial layers associated with the void surface. The evolution of this order parameter is shown to be governed by a form of the Cahn–Hilliard equation. An asymptotic analysis of the equation demonstrates, as intended, that the zero contour of the order parameter tracks the motion of a void evolving by diffusion under the coupled effects of stresses and the “electron wind” force. An implicit finite element scheme is used to solve the modified Cahn–Hilliard equation, together with equations associated with the accompanying mechanical and electrical problems. The diffuse interface model is applied to simulate a range of problems involving void evolution in interconnect lines. Results obtained are shown to be in excellent agreement with those computed previously using equivalent sharp interface models.

The Influence of Stress-Induced Voiding on the Electromigration Behavior of AlCu Interconnects

AbstractThe influence of stress-induced voiding on the electromigration (EM) behavior has been investigated on narrow via-line structures. For this purpose the EM performance of metal lines containing stress-induced voids already before the electrical operation has been compared with samples without stress-induced voids. We found, that pre-existing stress voids in the metal lines do not affect the activation energy Ea and lead only to a small decrease of the EM median time to failure, but cause a relevant reduction of the current density exponent down to n = 1. As a consequence, a tremendous decrease of the electromigration limited life time is obtained.

Stressmigration Behavior of Multilevel Ulsi Alcu-Metallizations

AbstractWith decreasing geometries of metal interconnects the demands on metallization reliability increase rapidly. In addition to electromigration, stress-induced voiding becomes a major problem, influencing lifetime and functionality of integrated circuits. This paper summarizes our studies on stressmigration behavior of various AlCu-multilevel metallizations. A model for an estimation of the median time to failure is presented.

Trade-off and process consideration for scalable poly-Si buffered LOCOS technology

The trade-off and process consideration for the scalable usage of poly-Si buffer LOCOS (PBL) technology has been studied. By using a proper stack layer of pad-oxide/poly-Si/nitride, an available and reliable PBL process for scalable device isolation can be achieved. A dual mechanism for pit formation is proposed. As the thermal stress is too large to be sustained by the pad poly-Si, stress-induced voids are found in the poly-Si layer after field oxidation. The residual stress would considerably damage the pad oxide, eventually leading to pit formation at the mostly stressed active area while removing the pad poly-Si. On the other hand, when the stress is not sufficiently high, the pad poly-Si is just subject to stress-enhanced oxy-nitridation. A proper etching control can be employed to retain the integrity of Si substrates. As results, thicker nitride induces larger stress and thus much more easily causes pit formation. Moreover, thicker pad poly-Si can sustain larger stress, but degrade the drain-induced barrier lowering for the field isolation device. Hence, the choice of the PBL stack layer is of great importance to reduce the bird's beak encroachment and alleviate the pit formation as well as retain the gate oxide integrity and the isolation performance.

A physically based model of electromigration and stress-induced void formation in microelectronic interconnects

In this article, a model of electromigration and stress-induced void formation in microelectronic interconnects is presented. This model solves the equations governing atomic diffusion and stress evolution in two dimensions, and can therefore account for the complex grain structures present in typical metal lines. A combined analytical and numerical solution scheme is developed to calculate the atomic fluxes and the evolution of mechanical stress, while avoiding the difficulties associated with finite element based approaches. Once a void has formed, growth is modeled by calculating the flux of atoms away from the void site. By combining models of atomic diffusion, stress evolution, void nucleation, and void growth, the complete void formation process can be simulated. To demonstrate this approach, void growth is calculated in interconnects where electromigration and thermal stress-induced damage have been experimentally observed. The results confirm that the model can quantitatively simulate void formation in realistic grain structures.

Void nucleation on intentionally added defects in Al interconnects

Void nucleation in passivated aluminum interconnects was studied using high voltage scanning electron microscopy. To test theories about stress-induced and electromigration void nucleation, Ar ions were implanted into Al specimens. The Ar atoms precipitated and formed bubbles that served as nucleation sites with high surface energy. In the implanted samples, voids formed away from the interconnect sidewalls, in contrast to voids in ordinary passivated Al interconnects. The evolution of the void volume was also affected by the reduction in the nucleation barrier. These results strongly support the theory of void nucleation on interface flaws in Al interconnects.

Modeling the effect of porosity on ductile fracture of powder processed titanium alloy

Ductile fracture of two-phase alloys occurs by initiation, growth and coalescence of voids which nucleate at second-phase particles. In this work, a model of void growth based on Wilkinson and Vitek crack theory was used to describe the crack propagation in powder metallurgically processed titanium alloy. In this model, the effect of the stress field of the residual pores on the growth and coalescence of the secondary voids was considered. The purpose is to provide useful insight to the influence of the residual pores after powder metallurgical processing and the subsequently stress-induced secondary voids on fracture of titanium alloys.

Indentation plastic displacement field: Part II. The case of hard films on soft substrates

The plastic displacements around Knoop indentations made in hard titanium/aluminum multilayered films on soft aluminum alloy substrates have been studied. Indentations were cross-sectioned and imaged using focused-ion-beam (FIB) milling and high-resolution scanning electron microscopy (SEM), respectively. The FIB milling method has the advantage of removing material in a localized region without producing mechanical damage to the specimen. The micrographs of the cross-sectioned indentations indicate that most of the plastic deformation around the indentation is dominated by the soft aluminum substrate. There is a very small change in the multilayered film thickness around the indentation—less than 10%. The plastic deformation of the thin film resembles a membrane being deflected by a localized pressure gradient across the membrane. Stress-induced voids are also observed in the multilayered film, especially in the area around the indentation apex. The density and the size of the voids increase with indentation depth. Indentation sink-in effects are observed in all of the indentations inspected. Based on the experimental results, the amount of sink-in of the hard film–soft substrate composite is larger than the bulk substrate and film alone. This is confirmed by the finite element analyses conducted in this work.

Stress-induced voiding in stacked tungsten via structure

Abstract The stress-induced voiding (SV) in Al-alloy films with stacked tungsten via structures was investigated. Voids were found in interconnections with stacked and borderless vias that had resistance increase after the aging tests. Failure occurs most frequently when the test structures are stored at approximately 250°C. This behavior can be explained by the diffusion creep model similar to SV in a flat line [1] . Finite-element simulations show that tensile stress in Al-lines between upper and lower plugs increases with temperature increase over 175°C. Al grains on W-plugs were found to have high-angle crystalline misorientation in transmission electron microscopy (TEM) observation. The tensile stress and grain misorientation should accelerate the void growth during high temperature storage. O 2 plasma post metal etch treatment is effective to eliminate SV in stacked via structure.

Metallurgical techniques for more reliable integrated circuits

One of the primary concerns in the manufacture of advanced microelectronic devices is to ensure that metallic contacts and interconnects do not fail by electromigration or stress-induced voiding. This article discusses the possibility of implementing two kinds of beneficial treatments within normal manufacturing processes—treatments that modify grain structure to minimize failures through diffusional flux divergence and treatments that control solute and precipitate distributions in order to avoid undesirable, overaged microstructures at the end of manufacturing.

Effects of pre-existing interfacial defects on the stress profile in aluminum interconnection lines

The profile of thermal stresses in aluminum interconnection lines, with the presence of local debonded areas between the line and the surrounding dielectric, is studied numerically. Local interfacial debonding is presumably due to contamination during the line patterning process. Various geometrical features of the interconnect and the debond segment are assumed, and the resulting stress fields are examined through two-dimensional (2-D) and three-dimensional (3-D) finite element analyses. It is found that interfacial debonding results in a local reduction of stress in aluminum, with the effect becoming larger as the line aspect ratio increases. The location of debond also influences the line stress. Implications of the findings to the interconnect reliability, particularly stress-induced voiding in aluminum lines, are discussed.

Investigation of the Homovalent Impurity in Aluminum to Form Alloys With Enhanced Interconnect Reliability

ABSTRACTDiffusion-induced failures such as stress-induced voiding and electromigration (EM) are a major concern for interconnect metallization in silicon integrated circuits. The addition of solute elements to aluminum interconnects often leads to “blocking” of high diffusivity paths such as grain boundaries and thus to an improvement in the resistance to electromigration failure. This research investigates Al-In, Al-La, and Al-In-La alloys to improve interconnect EM resistance. The choice of these alloying elements is based on the fact that they have negligible solid solubility in aluminum and are homovalent. Lower solubilities may lead to grain boundary stuffing and hence to improved EM resistance. In addition, the homovalency minimizes the adverse effect on the metal resistivity from addition of impurities to aluminum. Multicomponent diffusion principles are used to tailor aluminum-based ternary alloy compositions which would exhibit the multicomponent effect of zero flux planes (ZFPs), or regions in the reaction zone of a diffusion couple where the flux of a component goes to zero. This study involves modeling the occurrence of ZFPs for aluminum in several diffusion couples of Al-In-La, thus limiting the bulk diffusive spreading of aluminum so that the electromigration behavior can be inhibited or eliminated. This paper presents our experimental findings and discusses the modeling approach to determine ternary alloys exhibiting ZFPs.

In situ transmission electron microscopy study of plastic deformation and stress-induced voiding in Al–Cu interconnects

Plastic deformation in submicron wide Al-1 wt %Cu interconnects was studied in situ using a straining device in the transmission electron microscope. Dislocation motion occurred readily in unpassivated lines but was nonexistent in passivated lines due to the presence of stiff oxide sidewalls. Instead heterogeneous void nucleation occurred on straining to a critical limit. The void morphology was always near hemispherical and the nucleation always took place at the line edges. Further stretching of the lines led to a rupture of the sidewalls away from the lines, resulting in immediate dislocation motion. Void nucleation, cross slip, and operation of dislocation sources at line edges were all recorded on video. It was noted that dislocations almost parallel to the plane of the lines are rarely observed and furthermore, their movement is sluggish. Based on the dislocation configuration observed in these lines, a generalized geometrical model was arrived at in order to determine the significance of grain orientation on yield stress of passivated lines with columnar, bamboo grains. Frequent occurrence of twinning within the grains indicated that plastic deformation was indeed restricted in confined metal lines.

Electromigration and stress-induced voiding in fine Al and Al-alloy thin-film lines : C.-K. Hu, K.P. Rodbell, T.D. Sullivan, K.Y. Lee and D.P. Bouldin. IBM. J. Res. Develop., 1995, 39(4), 465

Electromigration and stress-induced voiding in fine Al and Al-alloy thin-film lines : C.-K. Hu, K.P. Rodbell, T.D. Sullivan, K.Y. Lee and D.P. Bouldin. IBM. J. Res. Develop., 1995, 39(4), 465

Linewidth dependence of stress relaxation and microstructural change in passivated Al(Cu) lines

Relaxation of thermally induced stresses in passivated line structures can lead to void formation, and its rate is strongly correlated with microstructural change in the lines. A bending beam technique was used to measure the thermal stress relaxation behavior of passivated Al (1 wt % Cu) line structures with 3, 1, and 0.5 μm linewidths as a function of temperature up to 15 h. Our data indicate that stress relaxation in Al(Cu) lines depends on line geometry and temperature, and exhibits log (time) kinetics, which is consistent with a thermally activated dislocation glide mechanism. The observed behavior can be explained by a combined result of the driving force due to the effective shear stress and kinetics due to thermally activated mass transport. Scanning electron microscope and transmission electron microscope techniques were used to study stress-induced voiding as a function of aging time and temperature. A strong correlation between stress relaxation rate and void density was observed for 1 μm wide lines, but not for 0.5 μm wide lines. A lower void density of 0.5 μm wide lines suggests that the bamboo grain structure may influence the mass transport and retard void formation.

Grain boundary misorientation angles and stress-induced voiding in oxide passivated copper interconnects

Grain boundary misorientations were determined by electron backscattering diffraction for tantalum-encapsulated, copper interconnects which contained thermal-stress-induced voids. The misorientation angles at voided and unvoided line segments were analyzed for two differently heat treated sample types, which were not equally susceptibile to stress voiding. Unvoided line segments contained a larger percentage of low misorientation angle, lower diffusivity boundaries than regions adjacent to voids. In addition, the more void resistant sample type also contained an overall higher proportion of low misorientation angle boundaries than the sample type which exhibited more voiding. The data provide further support for the importance of local variations in microstructure, which control the kinetics of stress void formation and growth.

In-Situ Tem-Investigation of Stress- and Electromigration- Induced Void Formation and Growth in Passivated Al-Interconnects

ABSTRACTIn-situ TEM observations on void formation and growth have been performed in passivated Al-lines in order to collect detailed microstructural data such as void number density, void size distribution, and growth rates as a basis for modelling stress relaxation and electromigration (EM) effects.The samples were 0.5mm long lines of 200nm thick Al with different widths (0.8, 1.6 and 2.4μm) passivated with 200μm thick SiNx. Additional experimental parameters were average grain size (0.5μm to more than 3μm, i.e. nearly perfect bamboo structure in the lines), relaxation time (0.1 to 20h) and temperature (20 – 300°C) and electromigration current density (without current up to ∼2MA/cm2).Measurements without current reveal that stress induced voids– develop after a temperature step of 50°C during cooling from 450°C and above. Upon heating from RT they start shrinking at 150°C and disappear completely at 350°C.– decrease in number and total relative volume but have constant mean void size with increasing number n of temperature cycles (n < 4)– show a strong dependence of their total relative volume on the microstructure (grain size, bamboo structure) which is strongly dependent on the anealing temperature for T ≥450° C.– show growth rates during isothermal annealing which are very dependent on relaxation time and temperature.Additional measurement with an applied electrical current, i.e. during an EM-test, show that nearly all the preexisting stress-induced voids– change their shapes and positions. This is dependent on electrical current density and time. Their frequently observed motion along the line (against the electron wind) was not neccessarily stopped by so-called blocking grains, i.e. grains without boundaries parallel to the line.– slightly change their total number but nearly maintain their total relative volume which is independent of current density or time.The collected statistical microstructural data are in good agreement with macroscopic stress relaxation results by wafer curvature and X-ray diffraction and recent in-situ stress measurement during an EM-test.