Stress-induced Trap Generation Research Articles

Analysis of Drain Linear Current Turn-Around Effect in Off-State Stress Mode in pMOSFET

The turn-around effect of drain linear current (Idlin) with stress time in a pMOSFET in the off-state stress is investigated. The degradation rate of Idlin increases to a maximum of 6.1% at 20 s of the stress time and then continuously decreases to 3.35% at 1000 s in the off-state stress. The turn-around effect is analyzed by comparing the degradation rates of the performance parameters (Idlin, Idsat, SS, and Vth) in the off -state and gate induced drain leakage (gidl) -state stress modes. The results indicate that the Idlin turn-around effect in the off-state stress, which occurs as an effect of the negative oxide charge (Qox) formation, is more significant than that of the interface trap (Nit) for short stress time (before 20 s), and the donor-like Nit formation has major effects compared to those of Qox over a long stress time (after 20 s). This observation shows that the stress-induced trap generation can be investigated even if the protection diode exists and critically impacts the drain current degradation and should be seriously considered in the reliability of a DRAM circuit.

Effect of Simultaneous Mechanical and Electrical Stress on the Electrical Performance of Flexible In-Ga-Zn-O Thin-Film Transistors.

We investigated the effect of simultaneous mechanical and electrical stress on the electrical characteristics of flexible indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs). The IGZO TFTs exhibited a threshold voltage shift (∆VTH) under an application of positive-bias-stress (PBS), with a turnaround behavior from the positive ∆VTH to the negative ∆VTH with an increase in the PBS application time, whether a mechanical stress is applied or not. However, the magnitudes of PBS-induced ∆VTH in both the positive and negative directions exhibited significantly larger values when a flexible IGZO TFT was under mechanical-bending stress than when it was at the flat state. The observed phenomena were possibly attributed to the mechanical stress-induced interface trap generation and the enhanced hydrogen diffusion from atomic layer deposition-grown Al2O3 to IGZO under mechanical-bending stress during PBS. The subgap density of states was extracted before and after an application of PBS under both mechanical stress conditions. The obtained results in this study provided potent evidence supporting the mechanism suggested to explain the PBS-induced larger ∆VTHs in both directions under mechanical-bending stress.

Systematic analysis of oxide trap distribution of 4H-SiC DMOSFETs using TSCIS and its correlation with BTI and SILC behavior

The spatial position and energy level of the effective oxide trap in SiC DMOSFET were investigated using Trap Spectroscopy by Charge Injection and Sensing (TSCIS) method. It was found that the oxygen vacancy traps at 1.7 eV above from the valence band of SiO2 make threshold voltage (Vth) shift under high negative gate bias stress condition. To further understanding the extracted oxide trap, the repetitive negative stress and recovery test at VG= ±40 V were executed. The results confirm that Vth and subthreshold swing (SS) change were caused by the process induced pre-existed hole traps instead of the stress induced trap generation. This hole trapping also reduced the Stress Induced Leakage Current (SILC) after the negative bias stress.

Effect of Ge interface control layer on the interfacial and electrical properties of TaYOx thin films on GaAs substrates

Effects of a Ge interface control layer on the electrical properties of RF sputter-deposited TaYOx on n-GaAs substrates are studied in detail. It is found that the incorporation of an ultrathin Ge layer in between TaYOx and GaAs substrate improve various electrical parameters such as interface state density, border trap density, frequency dispersion, leakage current density and flat-band shift thereby improving capacitor performance. The trapping of charge carriers in GaAs MOS capacitors during constant voltage stress has also been studied and the increase in gate leakage current observed during electrical stress is estimated and explained by taking into account the build up of trap charges and stress induced trap generation. The cross-section of traps is also estimated to be in the range of 10ź18 cm2. Such a small value for the capture cross-section implies that the generated traps are neutral centers which are probably responsible for trap-assisted tunneling during voltage stressing.

Effect of Al Doping on the Reliability of ALD HfO2

CMOS device scaling below the 22 nm technology node requires gate dielectric materials with superior properties to those of conventional high-k materials. It was found that, Al incorporation into HfO2 results in an increase in the transition temperature from amorphous to polycrystalline state (1-2). Improved thermal stability (2) and enhanced permittivity (3) by Al doping into ALD HfO2 was also reported. As a result of the improvement in film properties, improved equivalent oxide thickness (EOT) values, reduced gate leakage current, lower hysteresis and improved interface quality were also observed for Al doped HfO2 (4-6). However, intermixing of HfO2 and Al2O3 depends significantly on the stack structure, which results in variations in the stoichiometry in the film (7). The relative position of HfO2 and Al2O3 in HfO2/Al2O3bi-layer has a significant influence on positive charge formation in the dielectrics and also on the quality of the interfacial layer (IL) (8-10).In this work, we deposited and studied the reliability of 40 cycles ALD HfO2 doped with Al in the deposition process. The ALD thin film composition was measured by X-ray photoelectron spectroscopy (XPS). Thin films with Al/(Al+Hf)% composition ranging 0% to 8% were deposited and annealed at 800oC in N2 ambient. MOS capacitors were then fabricated with ALD TiN as the metal gate. The electrical measurements show that, devices with ~2% Al/(Hf+Al)% have an optimized performance with 17% lower EOT than undoped HfO2. The amount of positive charge and gate leakage current density were also evaluated for all devices.The reliability of these devices was monitored by subjecting them to a constant field stress at E= 27.5 MV/cm in the gate injection mode, where the applied voltage to the gate was modified according to the EOT to have equal field across all the dielectrics. Stress-induced trap generation in the dielectrics was observed due to bulk and interface defects. Trap formation followed a power law function with stress time. Observed stress induced flat-band voltage shift (Fig. 1) shows that devices with Al/(Hf+Al)% =2% have 36% reduction in the rate of trap generation as compared to HfO2, whereas degraded flat-band voltage shift was observed for devices with Al/(Hf+Al)% =7%. It can be inferred that an optimized Al concentration in HfO2can lead to an improvement of the device performance. In order to further understand the reliability characteristics we plan to evaluate the change in interface state density with stress and their time dependent dielectric breakdown (TDDB) characteristics. References M.-Y. Ho et al., Appl. Phys. Lett., 81, 4218 (2002). H. Y. Yu et al., Appl. Phys. Lett., 81, 3618(2002). P. K. Park et al., Appl. Phys. Lett., 89, 192905(2006). W. J. Zhu et al., IEEE Electron. Dev. Lett., 23(11), 649(2002). V. Mikhelasvili et al., Appl. Phys. Lett., 85, 5950(2004).Y.-K. Chiou et al., J. Electrochem. Soc., 154 (4) G99(2007).M. H. Cho et al., Appl. Phys. Lett., 81, 1071(2002).B. H. Lee et al., Appl. Phys. Lett., 76, 1926 (2000).L. G. Gosset et al., J. Non-Cryst. Solids, 303, 17(2002).W. Wang et al., J. Appl. Phys., 105, 064108 (2009).

Stochastic Modeling of Positive Bias Temperature Instability in High-$\kappa $ Metal Gate nMOSFETs

Positive bias temperature instability (PBTI) has become one of the major reliability concerns in the present day CMOS technology. The PBTI mostly degrades the performance of high- \(\kappa \) /metal gate (HK/MG) nMOSFETs and is dominated by time dependent stress induced trap generation. The PBTI models proposed so far in different literature are deterministic in nature and overlook the randomness of the temporal degradation of transistor threshold voltage, \(V_{\rm th}\) . In this paper, we present a stochastic model for PBTI to predict the behavior of HK/MG nMOSFETs under inversion mode stress. The model is scalable and is verified against experimental data from two different groups. Our model separately considers each trap to predict their impact on device performance. The simulations are carried out at accelerated voltage and temperature conditions and we noted the variations in \(V_{\rm th}\) . In addition, we have analyzed the impact of PBTI on the performance of a ring oscillator and concluded that the circuit speed suffers significant degradation due to this effect. We have also observed that the adverse effect of PBTI becomes more severe as we go deeper into the nanometer technology.

Profiling of Channel-Hot-Carrier Stress-Induced Trap Distributions Along Channel and Gate Dielectric in High-$k$ Gated MOSFETs by a Modified Charge Pumping Technique

To better understand the channel-hot-carrier (CHC)-induced reliability problems, a modified charge-pumping (CP) technique is proposed to characterize the distribution profiles of trap generation in MOSFETs with high- k gate-stack. The effects of gate leakage current on CP measurements were minimized to ensure the correct CP data. While applying dynamic drain bias, the gate-induced drain leakage current is also considered to get correct CP data. Through the CP with dynamic drain bias and various gate pulse frequencies, the profiling of CHC stress-induced interface- and border-traps can be achieved. The CHC stress-induced interface trap generation appears along whole the channel but that-induced border trap generation is mainly located above the pinchoff region near the drain and decreases dramatically toward the center of the channel. Thus, the CHC stress causes quite localized border trap generation at the gate-edge region inside the high- k dielectric. The reliability data measured by CP with different gate voltage swings confirm that CHC stress causes interface trap generation through whole the channel and significant border trap generation at gate-edge region.

Electrical characteristics of HfO2 films on InP with different atomic-layer-deposition temperatures

The effect of the deposition temperature (200, 250, and 300 °C) on the electrical properties of the atomic-layer-deposited [atomic layer deposition (ALD)] HfO2 films on InP was studied. A significant grain growth as well as an increase in the accumulation capacitance occurred by increasing the ALD temperature from 200 to 250 °C. However, a further increase to 300 °C degraded the electrical properties as verified by various electrical characterizations, including an accumulation capacitance lowering, a near-interface defect (trap) formation, and an increase in the electrical stress-induced new trap generation, due to a significant In out-diffusion to the HfO2 film side.

Interfacial and electrical properties of HfO2 gate dielectrics grown on GaAs by atomic layer deposition using different oxidants

In this paper, we examined the effects of two different oxidants (H2O and O3) used during the atomic layer deposition (ALD) of HfO2 films on GaAs, particularly focusing on its interfacial and electrical properties. In comparison with the H2O-based ALD process, the O3-based process produced a large amount of elemental As and Ga–O related bonds near the HfO2/GaAs interface due to its stronger oxidizing power. High interface state and border trap densities of the O3-based sample degraded the low-field electrical stability, which was confirmed by the capacitance and leakage current measurements under various voltage-stressing conditions. However, in terms of high-field stability, the O3-based sample showed a much stronger resistance to stress-induced trap generation than the H2O-based sample.

Stress-induced leakage current and trap generation in HfO2 thin films

Stress-induced leakage current (SILC) is studied in 10 nm HfO2 metal-insulator-metal capacitors. Three regimes are observed in the current-time characteristics, namely, (1) an absorption current, (2) a quasi linear increase of current with time (SILC), and (3) thermal breakdown. Magnitude of SILC is strongly correlated to the nature of the cathode (being large for TiN and weak for Pt and Au), showing that SILC is governed by electron injection. Recovery is observed when short-circuiting the samples, pointing out that SILC is a reversible phenomenon. Desorption current and SILC are not correlated, which indicates that different defects control the absorption current and SILC. SILC is ascribed to the generation of oxygen vacancies upon hot electron injection, while recovery is ascribed to the recombination of oxygen ions with vacancies. In the SILC regime, the current varies as Ktn (n = 1.15 at room temperature). Bias and temperature dependence of K and n are studied. The dependence of K on bias can be desc...

Characterization of Border Trap Density With the Multifrequency Charge Pumping Technique in Dual-Layer Gate Oxide

The multifrequency charge pumping (MFCP) experiments have been investigated by many research groups for the characterization of oxide traps in high-permittivity (high-κ ) dielectric metal-oxide-semiconductor field-effect transistor samples. In these previous studies, the duty cycle was changed for control of charging and discharging depths. In this paper, the spatial and energy distributions of border traps in the metal gate/high-κ dielectric/silicon dioxide (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) interfacial layer stack structure were characterized as a three-dimensional (3-D) mesh profile by using the MFCP technique. The presented MFCP technique was based on the frequency of the gate pulse in conjunction with the tunneling model of trapped charges and was not the duty cycle. The methodological basis and the accurate model were introduced for the analysis of the measured MFCP data in dual-layer gate oxide. The low-frequency noise measurement and the MFCP technique were used for the analysis of the constant gate bias stress induced trap generation, and the 3-D mesh profile of generating trap density was presented. Moreover, the energy distribution of stress-induced traps was investigated within high-κ, SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and high-κ/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface.

Tunneling component suppression in charge pumping measurement and reliability study for high- k gated MOSFETs

Although charge pumping (CP) is a powerful technique to measure the energy and spatial distributions of interface trap and oxide trap in MOS devices, the parasitic gate leakage current in it is the bottleneck. A CP method was modified and applied to high- k gate dielectric in this work to separate the CP current from the parasitic tunneling component in MOS devices. The stress-induced variations of electrical parameters in high- k gated MOS devices were investigated and the physical mechanism was studied by the modified CP technique. The stress-induced trap generation for devices with HfO 2-dominated high- k gate dielectrics is like mobile defect; while that with SiO 2-dominated ones is similar to the near-interface/border trap.

Process Engineering and Trap Distribution for Dielectric/Si Interfacial Layer in High-k Gated MOS Devices

The effects of interfacial layer at high-k dielectric/Si substrate formed by using stress-relieved pre-oxide (SRPO) treatment on electrical characteristics of MOS devices were studied in this work. The equivalent oxide thickness value could be scaled with reducing the thickness of the high quality IL. The reliability in terms of stress-induced leakage and stress-induced Vfb shift is clearly improved for MOS device with a SRPO treatment. Besides, the constant-voltage stress-induced interface trap generation in MOSFET was measured by charge-pumping techniques. The influences of stress and recovery on devices with HfO2 high-k dielectric are also compared. Results show that the stress induced Vth shifts can be separated into two stages, namely, trap filling and generation. The trap generation stage is only determined by the stress voltage and temperature.

Improved Retention Characteristic in Polycrystalline Silicon–Oxide–Hafnium Oxide–Oxide–Silicon-Type Nonvolatile Memory with Robust Tunnel Oxynitride

In this paper, we present a simple novel process for forming a robust and reliable oxynitride dielectric with a high nitrogen content. It is highly suitable for n-channel metal–oxide–semiconductor field-effect transistor (nMOSFETs) and polycrystalline silicon–oxide–hafnium oxide–oxide–silicon (SOHOS)-type memory applications. The proposed approach is realized by using chemical oxide with ammonia (NH3) nitridation followed by reoxidation with oxygen (O2). The novel oxynitride process is not only compatible with the standard complementary metal–oxide–semiconductor (CMOS) process, but also can ensure the improvement of flash memory with low-cost manufacturing. The characteristics of nMOSFETs and SOHOS-type nonvolatile memories (NVMs) with a robust oxynitride as a gate oxide or tunnel oxide are studied to demonstrate their advantages such as the retardation of the stress-induced trap generation during constant-voltage stress (CVS), the program/erase behaviors, cycling endurance, and data retention. The results indicate that the proposed robust oxynitride is suitable for future nonvolatile flash memory technology application.

Modified Percolation Model for Polycrystalline High-$ \kappa$ Gate Stack With Grain Boundary Defects

We modify the existing oxide breakdown (BD) percolation model in this letter to account for the presence of microstructural weakest link grain boundary (GB) defects in polycrystalline high-κ (HK) gate stacks. The different rates of the stress-induced leakage current degradation and oxide trap generation at the bulk and GB regions need to be accounted for in modeling the statistical nature of BD in HK dielectric thin films. Simulated results reveal the dominance of GB-related failures and the origin of the non-Weibull stochastics inherent in polycrystalline HK stacks. We also point to the inability of conventional percolation models with an assumed uniform defect generation to describe the failure statistics of current HK gate stacks.

Charge trapping and reliability characteristics of ultra-thin HfYO x films on n-GaAs substrates

Ultra-thin layers of the HfYO x gate dielectric were deposited on n-GaAs substrates by employing radio frequency (rf) sputter deposition system with a Si interface control layer sandwiched between the dielectric and semiconductor. The trapping/detrapping behaviour of charge carriers in the ultra-thin HfYO x /Si gate dielectric stack has been extensively studied during constant-voltage stressing (CVS) and compared with the results obtained from directly deposited HfYO x films on n-GaAs. The increase in gate leakage current observed during electrical stress is estimated and explained by taking into account the build up of trap charges and stress induced trap generation. Also, the capture cross-section of the generated traps is estimated. The variation of the trap centroid and the trapped charge density with injected influences have been investigated using constant current stressing (CCS) measurements. The dielectric breakdown and reliability of the dielectric films have been studied using constant-voltage stressing. A high time-dependent dielectric breakdown (TDDB, t bd ⩾ 1700 s) is observed for HfYO x gate dielectric with a silicon inter-layer under a high constant-voltage stress (8 V).

MOSFET characteristics with poly-Si/HfAlON gate stacks using ultra-thin UV-ozone interfacial oxide

This paper conducts a comprehensive evaluation of the electrical characteristics of the poly-silicon gated n-channel metal–oxide–semiconductor field-effect-transistor (nMOSFET) with hafnium–aluminum-oxynitride (HfAlON) gate dielectric with interfacial ultraviolet-ozone (UV-O 3) oxide or chemical oxide. Interfacial UV-O 3 oxide exhibits well-controlled interfacial properties due to self-saturated growth and thick-oxide-comparable density, which is beneficial to suppress interfacial re-oxidation and reduces surface roughness. Compared with interfacial chemical oxide, the interfacial UV-O 3 oxide obviously improves both gate insulating and interface characteristics, including breakdown voltage increments, reduced gate leakage current, and as-deposited traps. In addition, the HfAlON gate stack with UV-O 3 interface oxide also shows encouraging nMOSFET device performances, with a small subthreshold swing, high electron mobility, saturation drain current, and negligible stress-induced trap generation. The results clearly suggest that the high-density interfacial UV-O 3 oxide possess a high potential to be integrated with further high-k dielectric applications.

Study of trap generation in the Sc2O3/La2O3/SiOx gate dielectric stack by scanning tunneling microscopy

Through scanning tunneling microscopy, the rate of electrical stress induced trap generation in the vicinity of the tip/high-κ interface of the Sc2O3/La2O3/SiOx gate stack is observed to be much higher than that at the SiOx/Si interface, implying that the former is more susceptible to electrical stress induced wear out. This polarity dependence is discussed in the context of current trap generation models and is shown to be best explained by anode hot-hole effect induced by inherently lower surface plasmon threshold energy at the metal/high-κ interface and a higher hole trapping rate in the relatively thick high-κ.

Post-stress/breakdown leakage mechanism in ultrathin high-κ (HfO2)x(SiO2)1-x/SiO2gate stacks: A nanoscale conductive-Atomic Force Microscopy C-AFM

AbstractConductive atomic force microscopy (C–AFM) in ultra high vacuum (UHV) has been used to characterize charge trapping in ultrathin as–deposited oxide films of 2–4 nm (HfO2)x(SiO2)1-x/SiO2multilayer gate stacks. Pre– and post–stress/breakdown (BD) dielectric degradation is analyzed on a nanoscale. A systematic observation probes stress induced trap generation facilitating physical stack BD. Degradation is considered in terms of the pronounced localized leakage contribution through the high–κ and interlayer SiOx. Simultaneous nanoscale current–voltage (I-V) characteristics and C–AFM imaging illlutrates charge trapping/decay from the native or stress induced traps with intrinsic charge lateral propagation. A post–stress/BD constant voltage imaging shows effects of stress bias polarity on the BD induced topography and trap assisted nano–current variations. Physical attributes of deformed artifacts relate strongly to the polarity of electron injection (gate or substrate) so discriminating the trap generation in high–κ and interlayer SiOxrevealing non–homogeneous (dynamic) nature of leakage.

Electrical Characteristics of the HfAlON Gate Dielectric With Interfacial UV-Ozone Oxide

In this letter, the electrical properties of a HfAlON dielectric with UV-O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> interfacial oxide were comprehensively studied and then compared with those of a HfAlON dielectric with interfacial chemical oxide. In the comparison of dielectric characteristics including leakage current density, transconductance, subthreshold swing, saturation drain current, effective electron mobility, and constant voltage stress reliabilities, the results clearly indicate that high-density interfacial UV-O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> oxide is beneficial in reducing both bulk and interface traps as well as diminishing stress-induced trap generation, and possesses a high potential to be integrated with further high-kappa dielectric applications.