Process Engineering and Trap Distribution for Dielectric/Si Interfacial Layer in High-k Gated MOS Devices

Abstract

The effects of interfacial layer at high-k dielectric/Si substrate formed by using stress-relieved pre-oxide (SRPO) treatment on electrical characteristics of MOS devices were studied in this work. The equivalent oxide thickness value could be scaled with reducing the thickness of the high quality IL. The reliability in terms of stress-induced leakage and stress-induced Vfb shift is clearly improved for MOS device with a SRPO treatment. Besides, the constant-voltage stress-induced interface trap generation in MOSFET was measured by charge-pumping techniques. The influences of stress and recovery on devices with HfO2 high-k dielectric are also compared. Results show that the stress induced Vth shifts can be separated into two stages, namely, trap filling and generation. The trap generation stage is only determined by the stress voltage and temperature.