Wafer Stress Research Articles

Process-induced stress and microcrack nucleation in GaAs wafers

Breakage of GaAs wafers during device fabrication leads to reduced yield and decreased quality control. Historically, wafer breakage that is not attributable to human or equipment errors has been assumed to be due to poor quality wafers. We present evidence that the probability of breakage during sub-micron GaAs device fabrication is a function of dielectric film edge stress, and not necessarily dependent on the magnitude of a critical flaw in the as-received wafer. X-ray residual stress measurements, x-ray topographic imaging, and three-point bend fracture measurements are used to determine the nature and origin of wafer breakage during those fabrication steps which induce large mechanical or thermal stresses. Our data show that the processing sequences that most influence wafer breakage are SiN passivation deposition and rapid thermal annealing implant activation. These processes are primarily responsible for large residual stresses developed in the near-surface layers of the GaAs substrate. For microelectronic applications, the existence of high film edge stresses nucleates microcracks, which further reduces fracture strength. The combined effects of high residual stress and low fracture strength make SiN passivated wafers more fragile (as compared to SiON passivated wafers), and therefore more likely to break during device processing.

A reliability comparison of RTO and furnace thin SiO 2 layers: effect of the oxidation temperature

Three thermal oxidation methods aimed at growing thin SiO 2 films have been considered: Low temperature oxidation, O 2-diluted oxidation, and Rapid Thermal Oxidation (RTO). These procedures differ not only in their oxidation temperature but also in the thermal uniformity that is possible to achieve across the wafer. The electrical evaluation of the test capacitors show that longer times-to-breakdown are attained by the RTO samples for thicknesses down to 50 Å. The observed behaviour is explained in terms of the different mechanical stress levels in the different samples due to their different oxidation temperatures according to viscoelastic relaxation considerations and is further confirmed by the analysis of their FTIR spectra. Despite their better intrinsic breakdown features, RTO oxides exhibit more defect related failures that arise from wafer stress related problems due to the spatial thermal gradients that are characteristics of RTO operation.

Scaling wafer stresses and thermal processes to large wafers

Gravitational stresses limit maximum temperatures for processing semiconductor wafers. Allowable rates of heating and cooling are also limited by the combined affects of thermal and gravitational stresses, particularly in batch processing of stacked wafers. With increasing wafer diameter these limitations become more severe, requiring such measures as improved wafer support to maintain a desired processing temperature or increased wafer spacing to maintain desired rates of heating and cooling. These issues are addressed here through the derivation of scaling rules and engineering formulas relating allowable operating conditions to wafer dimensions. Gravitational stresses and displacements are first determined analytically for wafers supported by rings or at discrete points. The maximum operating temperature is then computed by comparing the calculated gravitational stresses with the temperature-dependent wafer strength. The difference between wafer strength and gravitational stress is used to determine the allowable thermal stress and allowable temperature variation across the wafer. Finally, an analytical model of radial heat transfer in a batch furnace is used to compute the maximum permissible rates of heating and cooling as a function of the instantaneous wafer temperature. Example calculations illustrate the dependence of maximum operating temperatures and allowable ramp rates on wafer dimensions, support geometry, and wafer spacing.

The Influence of Crystalline Orientation on the Photoelastic Property of {100} Gallium Arsenide Wafer.

We developed an optical birefringence measurement method that uses a photoelastic modulator and a polarized laser. A He-Ne infrared laser was utilized as the light source for measuring the birefringence in gallium arsenide wafers. In this paper we will explain the theory behind this method and the process of measuring the stress in GaAs wafers. The magnitude of the principal stress difference as well as the directions of the principal stresses were obtained simultaneously and quantitatively by using equipment developed for this study. The optical birefringences of stressed GaAs specimens were measured. From the experimental results, it was found that the photoelastic constant depended upon the crystalline orientations. Furthermore, the birefringence direction did not always coincide with the principal stress direction. The relationship between the principal strain difference and the retardation was obtained by the stress-strain analysis of a single GaAs crystal. That relationship was almost independent of the crystalline orientations and the birefringence direction was almost equal to the principal strain direction.

The effect of patterns on thermal stress during rapid thermal processing of silicon wafers

The presence of patterns can lead to temperature nonuniformity and undesirable levels of thermal stress in silicon wafers during rapid thermal processing (RTP). Plastic deformation of the wafer can lead to production problems such as photolithography overlay errors and degraded device performance. In this work, the transient temperature fields in patterned wafers are simulated using a detailed finite-element-based reactor transport model coupled with a thin film optics model for predicting the effect of patterns on the wafer radiative properties. The temperature distributions are then used to predict the stress fields in the wafer and the onset of plastic deformation. Results show that pattern-induced temperature nonuniformity can cause plastic deformation during RTP, and that the problem is exacerbated by single-side heating, increased processing temperature, and increased ramp rate. Pattern effects can be mitigated by stepping the die pattern out to the edge of the wafer or by altering the thin film stack on the wafer periphery to make the radiative properties across the wafer more uniform.

Surface quality of {111} side-walls in KOH-etched cavities

A number of potential causes for the observed roughness of the side-walls in anisotropically etched cavities for silicon pressure sensors are investigated. Wafer stress is found to be the primary cause, possibly enhanced by the presence of precipitates from which etching irregularities may be initiated.

Study of Biaxial Stress Induced by Cosputtered Thin Molybdenum Silicide Films in Silicon Single-Crystal Substrates

Bending of 25 mm-diameter (100) silicon wafers produced by 100 nm-thick cosputtered molybdenum–silicon films has been investigated just after deposition, after rapid thermal annealing and after etching of the deposits. Values of biaxial stress in the films were determined by the use of a widely used relation. The Mo:Si ratio in the as-deposited films was 89:11. Radii of curvature of substrates were measured by a double-crystal X-ray diffractometer. Blank wafers with three widely different radii of curvature (33, 62 and 250 m) were chosen as specimens and their curvatures were taken into account in the determination of the value of biaxial stress in wafers with deposits. All the wafers were convex when viewed from the polished surface side on which the films were deposited. Values of σ for wafers with as-deposited films were in the range 3 × 108 to 14 × 108 Nm−2 (tensile). Wafers with higher initial bending showed higher values of stress. Deposition led to degradation of perfection, as revealed by broadening of the diffraction curves and the contrast in the topographs. Rapid thermal annealing at 1273 and 1373 K (3–4 min) led to formation of the MoSi2 phase and to a notable relaxation of stress. The values of σ were in the range 1 × 107 to ~6 × 108 N m−2 (tensile). The value of the stress was lowest for the blank wafer with smallest bending. Annealing also improved the degree of crystalline perfection of the silicon. Experiments performed after etching of the annealed specimens showed no significant change in the radii of curvature.

The Effect of Multilayer Patterns on Thermal Stress During Rapid Thermal Processing

AbstractMultilayer patterns can lead to temperature non-uniformity and undesirable levels of thermal stress in silicon wafers during rapid thermal processing (RTP). Thermal stress can, in turn, cause problems such as photolithography overlay errors and degraded device performance through plastic deformation. In this work, the temperature and stress fields in patterned wafers are simulated using detailed finite-element based reactor transport models coupled with electromagnetic theory for predicting radiative properties of multilayers. The temperature distributions are then used to predict the stress fields in the wafer and the onset of plastic deformation. Results are presented for two generic two-dimensional axi-symmetric reactors employing single and double side illumination. The effect of patterns and processing parameters are explored, and strategies for avoiding pattern induced plastic deformation are evaluated.

Influence of Crystalline Orientation on Photoelastic Property of Si Single Crystal.

We developed an optical birefringence measurement method that uses a photoelastic modulator and a polarized laser. A He-Ne infrared laser was adopted as the light source for measuring the optical birefringence in gallium arsenide wafers. In this paper we explain the theory and the process of measurement of stress in GaAs wafers. The magnitude of principal stress difference and also the directions of the principal stresses were obtained simultaneously and quantitatively using our developed equipment. The optical birefringences of {100} GaAs stressed specimens were measured. From the experimental results, it was found that the photoelastic constant depended on the crystalline orientation and that the birefringence direction did not coincide with the principal stress direction. By stress-strain analysis of the GaAs single crystal, it was found that the birefringence direction coincided with the principal strain direction and that the relationship between the principal strain difference and the birefringence was independent of crystalline orientation.

Relaxation of Si-SiO/sub 2/ interfacial stress in bipolar screen oxides due to ionizing radiation

Current gain degradation due to ionizing radiation in complementary single-crystalline emitter bipolar transistors was found to grow progressively worse upon subjecting the transistors to repeated cycles of radiation exposure and high-temperature anneal. The increase in radiation sensitivity is independent of the emitter polarity or geometry and is most dramatic between the first and second radiation and anneal cycles. In parallel with the current gain measurements, samples from a monitor wafer simulating the screen oxide region above the extrinsic base in the npn transistors were measured for mechanical stress while undergoing similar cycles of irradiation and anneal. The oxide on the monitor wafer consisted of a 45 nm thermal layer and a 640 nm deposited layer. The results indicate that ionizing radiation helped relieve compressive stress at the Si surface. The magnitude of the stress change due to radiation is smaller than the stress induced by the emitter contact metallization followed by a post metallization anneal. Correlation of radiation sensitivity in the bipolar transistors and mechanical stress in the monitor wafer suggests that mechanical stress may be influential in determining the radiation hardness of bipolar transistors and lends validation to previously reported observations that Si-SiO/sub 2/ interfaces are increasingly more susceptible to radiation damage with decreasing Si compressive stress. Possible mechanisms for the observed changes in stress and their effect on the radiation sensitivity of the bipolar transistors are discussed.

Synchrotron White Beam Topography Studies of Residual Stress in SiC Single Crystal Wafers with Epitaxial Thin Films

ABSTRACTThe residual stress in a 6H-SiC wafer with a 3C-SiC epitaxial overlayer is determined by the technique of Synchrotron white beam x-ray topography (SWBXT). The short wavelength and high energy attributes of synchrotron radiation are exploited to very accurately determine the wafer curvature. Different approaches including absorption edge contour (AEC) mapping, multiple diffraction line (MDL) analysis and diffracted x-ray beam divergence (DXBD) analysis in both transmission and reflection geometry are demonstrated. The residual stress distribution is calculated from the wafer curvature measurement.

Determination of bending stress of Si wafer using concentrated load

The technique of concentrated load with a simple O-ring supporter is used to measure the deflection of Si wafers. The load varies so that the ratio of the deflection to the wafer thickness changes from 0 to 1. For some samples, this ratio goes up to 1.4 at which the samples are fractured. It is observed in the experiment that the stress of the wafer can be described by the linear deflection theory for small deflection. However, when the deflection is larger than 1/5 of the wafer thickness, nonlinear deflection theory should be used and the stress in the middle plane cannot be ignored anymore. The total stress for large deflection is approximately equal to the sum of the stress of a linear elastic plate and the stress in the middle plane. The experiment also shows that the bending strength of the Si wafer strongly depends on the surface conditions. Mirror finishing surface gives high mechanical strength.

Correlation of the Stress-Temperature History with Microstructure in A1-0.5Cu and A1-0.15Pd Thin Films

AbstractBlanket films (1 μm thick) of both A1-0.5Cu and A1-0.15Pd were deposited at room temperature, 150°C, and 300°C. Stress in the as-deposited wafers increased with substrate temperature, as expected from the thermal expansion mismatch on cooling. All conditions were tiicrmally cycled to 450°C three times while continuously monitoring stress. The shapes of the curves were different for the two alloys because precipitates dissolve and reprecipitate in AlCu, but are present over the entire temperature range in AlPd. Lesser differences were evident comparing the stress-temperature behavior for the various substrate temperatures within a single alloy. The precipitate structure also influences the grain growth during thermal cycling, where substantially larger median grain sizes are found in AlCu compared to AlPd.

Optical, Electrical, and Mechanical Characterization of Rapid Thermal Oxidation

ABSTRACTIn this study, 6-150mm p-type <100> wafers were cleaned, laser-scribed, and pre-process measured for stress. The wafers were then processed in a tungsten-halogen lamp RTP system with a target Rapid Thermal Oxidation (RTO) thickness of 100Å. Three categories of whole-wafer measurement techniques were used to characterize these wafers: optical, electrical, and mechanical. Optical inspection techniques included spectroscopic reflectometry (reflectivity), and a combination of beam profile reflectometry and beam profile ellipsometry (thickness). Electrical techniques included C-V plotting with a mercury probe (oxide thickness from Cmax, breakdown voltage, and interface trap density) as well as laser-induced photo-current scanning (minority carrier lifetime, minority-carrier diffusion-length). Mechanical inspection included wafer warpage and stress measurements as well as optical imaging inspection using the magic mirror method (damage and defects). Wafer measurements from these instruments (i.e., contour and 3-d maps) are used to characterize integrity of the RTO process.

Effect of wafer stress on surface photovoltage diffusion length measurements

The surface photovoltage technique is an attractive method for measuring the minority carrier diffusion length. It has the advantage of not requiring permanent sample contacts. It does require, however, an accurate knowledge of the absorption coefficient-wavelength relationship. This relationship is well known for single-crystal silicon. However, for polycrystalline silicon we find the single-crystal data not to be applicable over the wavelength range for SPV measurements. We observe nonlinear SPV plots when using the well known α-λ data. Depending on which portion of the plot is used for diffusion length determination, one can obtain very different diffusion lengths. By making SPV, short circuit current, and spectral response measurements and comparing theory with experiment, we find a new α-λ relationship which is dependent on the stress in the sample. Since this stress varies spatially, it is difficult to use one particular set of α-λ data for SPV interpretation. We can find the low wavelength range of SPV plots to be most suitable for diffusion length measurements.

Characterization of stress in semiconductor wafers using birefringence measurements

The nondestructive optical method for quality control based on measurement of birefringence in semiconductor wafers is described. The influence of crystallographic orientation and multiple reflections in wafers on measured parameters are discussed. Also the full description of the device used for investigation of commercial semiconductor wafers is given. The last part of the article is devoted to the results of experimental investigations of semiconductor wafers during manufacturing of semiconductor devices and IC

Analysis of stresses in GaAs single-crystal wafers by X-ray diffraction and photoelasticity methods

The stress data in GaAs wafers measured by the photoelasticity technique are compared with strain data measured by the X-ray diffraction. For a Czochralski-grown undoped single crystal both methods provide the determination of elastic strains and stresses caused by dislocations. In a strongly silicon-doped single crystal grown by horizontal Bridgman technique, X-ray measurements reveal the lattice parameter variations along the wafer due to the dopant, whereas the photoelasticity method provides the determination of elastic strains and stresses due to inhomogeneous dopant distribution. Comparing the data obtained by these two techniques, it is possible to separate the elastic lattice distortions caused by dislocations and/or inhomogeneity in the dopant distribution from the effect on the lattice parameter caused by the dopant proper. The sensitivity and the information capacities of both methods are compared. [Russian Text Ignored]

Two-dimensional state of stress in a silicon wafer

Two-dimensional state of stress in (001) and (111) silicon wafer is studied with infrared photoelasticity. In two widely used groups of coordinate systems, the silicon piezo-optical coefficient tensors due to photoelastic anisotropy of silicon crystal are derived. The relation between stress ellipsoid and refractive index ellipsoid is analyzed with infrared polarized light transmitting through the silicon crystal in certain directions. The applicability of the stress-optical law in (001) and (111) silicon wafers is presented. A three direction observation method is developed to decide the magnitude and direction of principal stresses in silicon wafer. The stress states in (100) and (111) silicon wafers after certain device processes are also measured and calculated. Comparisons of experimental and calculated results are made.

Stress and Plastic Flow in Silicon During Amorphization by Ion-Bombardment

ABSTRACTThe in-plane stress in silicon wafers during amorphization by ion-bombardment was determined from wafer curvature measurements using an in-situ laser scanning technique. Measurements were made during room temperature bombardment with 2 MeV Ne, Si, Ar, Kr, and Xe ions. In all experiments, compressive stress was built-up in the bombarded region as a function of the fluence, until a maximum was reached at the dose required to form amorphous silicon. During further amorphization by bombardment, the stress decreased and eventually stabilized. If ion bombardment was interrupted during amorphization, a stress increase was observed over a period of several minutes; when the beam was turned on again, the stress returned immediately to the value measured before interruption. Step height measurements were performed on implanted wafers to determine the out-of-plane strain, and RBS was used to determine the damage profiles. A model is proposed that describes the behavior in terms of the expansion of crystalline silicon by the creation of defects and the flow of amorphous silicon under the ion beam.

Non-destructive determination of residual stresses in circular silicon wafers

Non-destructive determination of residual stresses in circular silicon wafers