Static Random Access Memory Bitcell Research Articles

Investigating the Impact of Technology Scaling on Stability Performance of Sub-threshold Static Random Access Memory Bitcell Topologies

Static random-access memory (SRAM) is increasingly being used in VLSI circuits as a result of the development of portable devices. As the demand for low-power devices increases, sub-threshold operation of SRAMs has become a popular method to reduce power consumption but at the cost of reduced stability. The work aims to propose design parameters for SRAM bit cell topologies- 6T and 10T with proper device sizing and to investigate the impact of technology scaling on its stability performance in the sub threshold region. Moreover, analysis demonstrates the impact of variations of device sizing in terms of Cell ratio and Pull up ratio on stability margins of designed SRAM topologies. Simulations are carried out in the HSPICE environment using 16 nm and 22 nm CMOS process nodes. We find that the stability margins of 10T SRAM cell outperform the 6T SRAM cell; however stability margin decreases with decreasing technology nodes. The Read Static Noise Margin (RSNM) and Write Static Noise Margin (WSNM) of 10T SRAM cell is improved by 48.38% and 308.64% respectively in 22nm and 53.04% and 243.93% respectively in 16nm process technology as compare to 6T SRAM cell.

Design of High-Speed, Low-Power Sensing Circuits for Nano-Scale Embedded Memory.

This paper comparatively reviews sensing circuit designs for the most widely used embedded memory, static random-access memory (SRAM). Many sensing circuits for SRAM have been proposed to improve power efficiency and speed, because sensing operations in SRAM dominantly determine the overall speed and power consumption of the system-on-chip. This phenomenon is more pronounced in the nanoscale era, where SRAM bit-cells implemented near minimum-sized transistors are highly influenced by variation effects. Under this condition, for stable sensing, the control signal for accessing the selected bit-cell (word-line, WL) should be asserted for a long time, leading to increases in the power dissipation and delay at the same time. By innovating sensing circuits that can reduce the WL pulse width, the sensing power and speed can be efficiently improved, simultaneously. Throughout this paper, the strength and weakness of many SRAM sensing circuits are introduced in terms of various aspects-speed, area, power, etc.

A 47 TOPS/W 10T SRAM-Based Multi-Bit Signed CIM With Self-Adaptive Bias Voltage Generator for Edge Computing Applications

This paper presents a 10T static random-access memory (SRAM) -computing in memory (CIM) structure of 32kb macro unit for convolutional neural networks (CNNs). The proposed CIM handles ± computation with signed input signals in a single bitcell and obtains 3 times BL range for a larger sensing margin. Although the area overhead of the SRAM bitcell is 27 larger due to the positive branch PMOS, the array size is reduced to half for the same computation. A serial multi-bit weight technique is used to extend the number of weight bits with improved linearity and no significant time penalty. A bias voltage generator is implemented to regulate the discharge current under different PT variations. Both weight and input can be adjusted to 1, 2, and 4-b. For 4-b weight and 4-b input, the proposed structure achieves 85.7% accuracy with the CIFAR-10 dataset and 47 TOPS/W energy consumption in CMOS 28nm technology.

3D SRAM Macro Design in 3D Nanofabric Process Technology

In this paper, we introduce a novel design of a 3D static random-access memory (SRAM) macro in a 3D Nanofabric process technology. The 3D Nanofabric technology is based on enabling the processing of N stack of identical layers simultaneously regardless of the number of stacked layers which consequently reduces the fabrication cost as well as the footprint of SRAM macros. To enable simultaneous patterning of stacked layers, 3D Nanofabric requires circuit topology and layout that rely on a single layer where the device channel, poly, and metal wires are all embedded without any other crossing than the gate on top of the device channel. Accordingly, we modify the layouts of the conventional SRAM bit-cell and periphery circuits which are complex and contain several metal crossings. Furthermore, we propose a new overall organization of the 3D SRAM macro that incorporates a stack of multiple identical layers each consisting of an equal size 2D array of bit-cells and the periphery circuits. We show that the proposed 3D Nanofabric SRAM macro offers 71.2% footprint gain and 36.3% read access speed improvement compared to equal size 2D SRAM macro in 3 nm FinFET.

Stability and Power Analysis of Schmitt Trigger Based Low Power SRAM Bit-Cell Using CMOS and CNTFET Technology at 22nm Technology Node

SRAM (Static Random Access Memory) is an essential component of memory devices such as laptops, phones, etc., which act as a semiconductor memory. The “Carbon Nanotube Field Effect Transistor (CNTFET)” is silicon associated high-stability, low-power device with excellent performance. CNTFET has been verified to be very advantageous for Very large-scale integration circuit designs in the nanoscale range because of its remarkable properties of metal oxide semiconductor field effect transistor (MOSFET). The material was brought to light because of its genuinely incredible electrochemical performance. Carbon nanotubes have unique properties such as high charge carrier mobility, high voltage, small footprint, exceptionally short and high control over pulse duration, and large current densities. In traditional MOSFET, bulk silicon is used, which has high leakage current and high field-effect; thus, CNTFET has been used as an alternative in recent years. When compared to the 10T CNTFET SRAM Bit cell is designed using HSPICE Tool in 22nm technology. Long-term stability and significant process variable changes are significant challenges with nanoscale SRAM cells.

BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory

This work presents BP-SCIM: a reconfigurable 8T static random access memory (SRAM) macro for bit-parallel searching and computing in-memory (CIM). The decoupled read/write ports of the employed 8T SRAM bit-cell eliminate read disturbance during search and CIM operations. BP-SCIM can support both in-memory Boolean logic and arithmetic operations. Novel CIM-friendly algorithms and peripheral circuits are proposed to reduce the latency of complex arithmetic operations such as multiplication and division. In addition, BP-SCIM can be configured as either a binary content-addressable memory (CAM) or a ternary CAM for fast searching. A 256 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 64 BP-SCIM test chip was implemented in 65-nm CMOS technology. The 8-bit addition and 8-bit multiplication operations can achieve the maximum energy efficiency of 3.11 TOPS/W and 0.17 TOPS/W, respectively at 0.7 V supply. For the binary CAM search operation, BP-SCIM can achieve the minimum energy consumption of 0.91 fJ/bit/search at 87 MHz and 0.8 V supply.

In-Memory Computation With Improved Linearity Using Adaptive Sparsity-Based Compact Thermometric Code

The article presents an efficient static random access memory (SRAM)-based in-memory computation (IMC) architecture which is capable of performing image classification with improved linearity. In this work, we proposed a thermometric code-based IMC (TC-IMC) to perform multibit multiply-and-accumulate (MAC) operations with improved linearity. An input sparsity-aware compact thermometric code approach is proposed to reduce the number of SRAM bitcells compared to the thermometric code-based encoding without loss of accuracy in the MAC operation. We proposed an optimal sampling time to improve the linearity of the TC-IMC MAC operation with maximum signal margin (SM) based on the detailed nonlinearity analysis of 8T SRAM-based TC-IMC architecture. The test chip measurement results in 180 nm process show that the proposed TC-IMC has 72% better linearity than the traditional IMC. The measured results on 100 Modified National Institute of Standards and Technology (MNIST) and CIFAR-10 test images show an accuracy of 97% and 87%, respectively. In addition, the proposed TC-IMC architecture achieves MAC compute latency of 25 ns, GOPS/kb (normalized to 1 b <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 1 b) of 29.8, and energy efficiency of 2.3 TOPS/W. The simulation result of the entire 10000 MNIST and CIFAR-10 images considering process variation effects shows an accuracy of 98.7% and 90.4%, respectively.

FinFET based SRAMs in Sub-10nm domain

An exponential rise in transistor count, have increased the power consumption of the modern digital system. Moreover, at lower technology node, the performance of conventional CMOS designs degrades because of the short channel effects (SCEs). In sub-10 ​nm technologies, FinFET devices have good gate control and achieve superior performance than CMOS designs. FinFET devices possess high ION current and improved scalability compared to conventional CMOS. Among numerous double gate (DG) devices, the quasiplanar FinFET structure gained huge attention because of the simple fabrication process [4]. However, FinFET based designs have a major width quantization issue. The width of FinFET device varies only in quanta of silicon fin height (HFIN) [4]. This is a critical issue for ratioed designs like Static Random-Access Memory (SRAMs), where proper sizing of transistors is essential for correct functionality. With process variations, this issue becomes even worse and affect the performance of SRAM cell. The SRAM has a significant performance impact on current nanoelectronics systems. Next-generation devices overcome the short-channel effects (SCE) of CMOS technology and can be used to improve the efficiency of SRAM designs. FinFETs are promising emerging devices, which can improve the performance of SRAM designs at lower technology nodes. This review paper presents different types of SRAM bitcells and memory system architectures. It also discusses the detailed analysis of SRAM bitcells based on various highly explored FinFET devices in sub-10nm domain. The read stability and write ability of SRAM cells are determined using Static Noise Margin (butterfly) and N-curve methods. Moreover, this manuscript presents a benchmarking between the Underlapped FinFET based SRAM and Design Technology Optimized FinFET Based SRAM. In addition to this, Monte Carlo simulations are performed on the SRAM cells to evaluate process variations to determine the robustness of SRAM designs. Simulations were done in HSPICE using 7 ​nm technology.

Single-Event Multiple Effect Tolerant RHBD14T SRAM Cell Design for Space Applications

Static Random Access Memory (SRAM) is primarily used as a memory storage element, which is susceptible to radiation-induced Single Event Upsets (SEUs). Hence, a robust SRAM bit-cell design is primarily a difficult task to address the space radiation environment. Furthermore, as the transistor’s size moves into nanometer regimes, a new challenge like Single Event Multiple Effects (SEME’s) evolved in SRAMs. SEME’s make the design of SRAM a serious challenge. In this article, a novel Radiation Hardened By Design (RHBD) SRAM bit-cell is proposed based on the polarity upset mechanism of SEUs. This work shows that the proposed RHBD14T SRAM bit-cell is SEU immune and delivers higher SEME critical charge than state-of-the-art RHBD SRAM bit-cells. The Monte Carlo (MC) simulations further show that the proposed RHBD14T SRAM delivers the lower Probability of Failure when compared to reported RHBD SRAM cells. Consequently, the proposed bit cell’s sensitive area is 128% lower with respect to the recently reported state-of-the-art RHBD RSP14T SRAM bit-cells.

Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation

Near-threshold voltage ( $V_{th}$ ) operation is an effective method for lowering energy consumption. However, it increases the impact of $V_{th}$ variation significantly, which makes it difficult for previously proposed static random access memory (SRAM) bitcells to achieve high read stability and write ability yields. To achieve these in the near- $V_{th}$ region, a differential 7T SRAM bitcell is proposed in which an additional row-based control signal and an nMOS transistor between the pull-up and pull-down transistors is adopted on one side of the cross-coupled inverter. In addition, the proposed SRAM bitcell can use a bit-interleaved structure without the half-select issue. Compared to differential 10T and 12T SRAM, the proposed differential 7T SRAM achieves 5% and 6% higher SRAM operating frequency and 70% and 23% lower operation energy consumption with a 33% and 49% smaller bitcell area, respectively.

10T SRAM Computing-in-Memory Macros for Binary and Multibit MAC Operation of DNN Edge Processors

Computing-in-memory (CIM) is a promising approach to reduce latency and improve the energy efficiency of the multiply-and-accumulate (MAC) operation under a memory wall constraint for artificial intelligence (AI) edge processors. This paper proposes an approach focusing on scalable CIM designs using a new ten-transistor (10T) static random access memory (SRAM) bit-cell. Using the proposed 10T SRAM bit-cell, we present two SRAM-based CIM (SRAM-CIM) macros supporting multibit and binary MAC operations. The first design achieves fully parallel computing and high throughput using 32 parallel binary MAC operations. Advanced circuit techniques such as an input-dependent dynamic reference generator and an input-boosted sense amplifier are presented. Fabricated in 28 nm CMOS process, this design achieves 409.6 GOPS throughput, 1001.7 TOPS/W energy efficiency, and a 169.9 TOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> throughput area efficiency. The proposed approach effectively solves previous problems such as writing disturb, throughput, and the power consumption of an analog to digital converter (ADC). The second design supports multibit MAC operation (4-b weight, 4-b input, and 8-b output) to increase the inference accuracy. We propose an architecture that divides 4-b weight and 4-b input multiplication to four 2-b multiplication in parallel, which increases the signal margin by 16× compared to conventional 4-b multiplication. Besides, the capacitive digital-to-analog converter (CDAC) area issue is effectively addressed using the intrinsic bit-line capacitance existing in the SRAM-CIM architecture. The proposed approach of realizing four 2-b parallel multiplication using the CDAC is successfully demonstrated with a modified LeNet-5 neural network. These results demonstrate that the proposed 10T bit-cell is promising for realizing robust and scalable SRAM-CIM designs, which is essential for realizing fully parallel edge computing.

Design of multi-cell upset immune single-end SRAM for low power applications

The on-chip static random access memory (SRAM) has been under revamp due to swift growth in demand of power-efficient internet-of-things based devices. In this context, a low power transmission gate based read decoupled 9-transistor (TRD9T) SRAM bit-cell has been proposed in this work. The proposed cell efficiently minimizes the power dissipation in terms of static/dynamic power and maintains the stability during read, write and standby mode as compared to five recent reported designs. The proposed cell is less vulnerable to soft errors due to improved critical charge that is followed elimination of half-select issue that facilitates bit-interleaved implementation. In addition to conventional 6T (Conv.6T) SRAM, it has been compared with five already reported designs such as tunable-access 8T (TU8T), single ended disturb free 9T (SEDF9T), P-P-N based 10T (P10T), low power 10T (LP10T) and data dependent 11T (D11T) bit-cells, for evaluating the relative performance of proposed design in terms of key design metrics. The reduction in soft error in proposed design is indicated by 1.14×/1.07×/0.99×/1.39×/1.05× improvement in critical charge in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T respectively. The proposed cell mitigates half-select issue to achieve the capability of implementing bit-interleaved architecture. Moreover, standby power of proposed design is reduced by 2.01×/2.46×/1.58×/0.79×/1.89×/1.90× in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T/D11T respectively and this improvement sustains at temperature variation from at 27 °C to 110 °C. The TRD9T exhibits 1.97×/1.87×/1.01×/1×/1.01×/1.78× higher read static noise margin and 1.17×/1.21×/1.44×/1.44×/1.11×/0.85× higher write static noise margin in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T/D11T respectively. Also, 1.70×/1.29×/2.09×/1.49×/1×/1.60× and 1.48×/1.77×/2.75×/1.77×/1.64×/2.28× improvement in read power and write power respectively is achieved in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T/D11T. The read access time of proposed design is improved by 1.31×/1.01×/2.12×/1.18×/1.01×/1.13× in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T/D11T. Proposed TRD9T show narrower variability in read stability, read power and read current in comparison to conv. 6T. The proposed TRD9T also exhibits best Electrical quality metric (EQM) among the cells considered in this work.

Noise-Immune 6T SRAM Bit-Cells Based on Side-Contacted FED

Modern system-on-chip (SoC) designers are trying to include more considerations in designing building blocks to present reliable integrated digital circuits as well as high-density ones. In this article, an innovative static random access memory (SRAM) bit-cell architecture is successfully designed based on the previously proposed side-contacted field effect diode (S-FED) using 180-nm technology. The device structure is optimized to satisfy high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio more than seven orders of magnitude. Behavioral modeling of S-FED in comparison with CMOS counterpart provides the capability of employing S-FED in the pull-down, pull-up, and pass-gate networks with identical geometry. The simplest triple S-FED-based bit-cell is designed to evaluate write and read logic 0/1 operations utilizing steady-state responses. Transient and ac analysis are also extracted from the six S-FED-based bit-cell to characterize SRAM fingerprints. Results demonstrate that the proposed bit-cell is noise-immune with maximum static noise margin (SNM) equal to 33.6% V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , high-speed with switching frequency of about 1.8 GHz (write) and 50 MHz (read), and low-power with static and dynamic power consumption lower than 10 nW and 5 nW/GHz, respectively. Moreover, SNM and Monte Carlo (MC) analyses reveal outstanding stability of the designed SRAM bit-cell based on S-FEDs when extreme variability scenarios induce device degradation.

Reverse Bias Current Eliminated, Read-Separated, and Write-Enhanced Tunnel FET SRAM

The reverse bias current of the tunneling field-effect transistor (TFET) could cause serious damage to static random-access memory (SRAM) circuit performance. To address this issue, a novel reverse bias current eliminated, read-separated, and write-enhanced TFET 12T SRAM bitcell is proposed for ultra-low power applications in this brief. It can prevent reverse bias currents, increase the hold/read static noise margin (H/RSNM) and dramatically decrease the static power consumption. The static power consumption of the proposed bitcell is reduced by four orders of magnitude compared with that of the 7T bitcell, demonstrating its great potential for ultra-low power applications. At a supply voltage of 0.6 V, the H/RSNM of the proposed bitcell is 25% larger than that of the 7T bitcell. It also includes a write assist circuit, thus increasing its write static noise margin (WSNM) and considerably decreasing its write power consumption. The WSNM of the proposed bitcell is more than twice that of the 7T bitcell, and is 60% larger than that of the combinational access bitcell. In addition, the write power consumption of the proposed bitcell is reduced by 95% compared with that of the combinational access bitcell at a supply voltage of 0.6 V. In terms of layout, the area of the proposed 12T bitcell is 92% larger than that of the 7T bitcell, but is 6% smaller than the area of the combinational access bitcell.

Performance comparison of 6T SRAM bit-cells based on side-contacted FED and CMOS

Designing a Static Random-Access Memory (SRAM) cell configuration that copes with conventional complementary metal-oxide-semiconductor (CMOS) constraints on the cell area is desired to satisfy high packing density in integrated digital circuits. This paper analyzes and compares performance parameters of 6T SRAM bit-cells based on the side-contacted field-effect diode (S-FED) and conventional CMOS at 180 nm technology node. Steady-state responses demonstrate that in the worst-case, by applying weak logic 0/1 to the bit-lines, strong logic data is stored in the S-FED-based cell with superior write margin and lower power consumption by about one order of magnitude in comparison with the CMOS-based one. Comparing static noise margin reveals that S-FED-based cells enjoy prominent stability, especially in the read and hold operations with ~3X and 29% improvements, respectively, to the CMOS-based versions. In addition, enhancement of read-stability is attained utilizing S-FED-based cell, as well as decrement of subthreshold current and static power dissipation, compared with the CMOS-based one. Sensitivity analyses extracted from Monte Carlo simulations and butterfly curves indicate that S-FED-based cell successfully tolerates process and supply voltage variations in all operation modes, superior to the CMOS-based counterpart.

A highly stable reliable SRAM cell design for low power applications

The growth in demand for power-efficient neural network accelerators has generated an intense demand for low power static random access memory (SRAM). In this context, a power-efficient transmission gate based 9-Transistor (TG9T) SRAM bitcell has been proposed in this work. In order to assess the relative performance of the proposed design in terms of major design metrics, it has been juxtaposed with contemporaneous designs such as the feedback-cutting 7T, fully differential 8T (FD8T) and single-ended disturb free 9T (SEDF9T) bitcells, while the reliability of such SRAM designs when subjected to process variations has also been analyzed. In terms of read stability (RSNM), the TG9T shows 2.87×/3.36× higher RSNM and 2.90×/2.67× narrower spread in RSNM, respectively, as compared to 7T/FD8T. In addition, it also exhibits 1.4×/6.55× higher write ability (WSNM) and 1.01×/5.05×/1.06× narrower spread in WSNM when compared with FD8T/SEDF9T and FD8T/SEDF9T/7T respectively. Moreover, a 1.15×/1.06× narrower spread in read delay (TRA) and 1.54×/1.38× narrower spread in read current (IREAD) are also exhibited by the proposed design in comparison with 7T/FD8T. The reliable nature of TG9T is indicated by the narrower spread in read stability, write ability, read delay and read current. Furthermore, in comparison with 7T/FD8T, TG9T consumes 2.92×/1.04× lower hold power. Additionally, the proposed cell shows 10.80×/17.81× lower write power consumption and 1.43×/18.37× lower read power consumption when compared to that of SEDF9T/FD8T and 7T/FD8T respectively. Amongst all SRAM bitcells used for comparison, the proposed bitcell yields the lowest VDD,min. The TG9T cell achieves all the aforementioned improvements at the cost of 1.22×/1.34× longer TWA and 1.93×/1.93× longer TRA when compared with 7T/SEDF9T and 7T/FD8T, respectively, at a supply voltage of 0.7 V.

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

We propose a highly symmetrical 10 transistor (10T) 2-read/write (2RW) dual-port (DP) static random access memory (SRAM) bitcell in 28 nm high-k/metal-gate (HKMG) planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves the robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (Iread) and read static noise margin (SNM) are respectively boosted by +20% and +15 mV by introducing the proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) N-channel MOSs (NMOSs). The minimum operating voltage (Vmin) of the proposed 256 kbit 10T DP SRAM is 0.53 V in the TT process, 25 °C under the worst access condition with read/write disturbances, and improved by 90 mV (15%) compared with the conventional one.

Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation

Conventional static random access memory (SRAM) suffers from high leakage power when implemented in advanced CMOS nodes, while modified bitcells or assist techniques are required to achieve robust low-voltage operation. Gain-cell eDRAM (GC-eDRAM) is an interesting area-efficient alternative to SRAM, but requires refresh cycles and typically a boosted write word-line (WWL). This brief proposes a hybrid GC-eDRAM/SRAM bitcell addressing the leakage power and low voltage robustness issues of SRAM, while avoiding bandwidth-consuming refresh and WWL boost of conventional GC-eDRAM. In the hybrid 8T bitcell, an SRAM keeper latch is connected to the storage node (SN) of a gain cell. The SRAM keepers are power gated most of the time for leakage reduction; the keepers are powered on only during zero bandwidth consuming refresh cycles, after write, and before read, to ensure strong data levels on the SN. Compared to a conventional 6T SRAM bitcell, the hybrid 8T bitcell has a 2T read port and an interruptible keeper for both robust read and write at low voltages. Simulations in 65-nm CMOS show that the hybrid bitcell enables 35% (at 400 mV) to 55% (at 1 V) lower data retention power than an 6T SRAM cell at 25 °C.

High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques

In this paper, we present a high-density four-transistor (4T) static random access memory (SRAM) bitcell design for 3-D CoolCube technology platform based on 14-nm fully depleted - silicon on insulator MOS transistors to show the compatibility between the 4T SRAM and the 3-D design and the considerable density gain that they can achieve when combined. The 4T SRAM bitcell has been characterized to investigate the critical operations in terms of stability (retention and read) taking into account the postlayout parasitic elements. Thus, failure mechanisms are exposed and explained. Based on this paper, a data-dependent dynamic back-biasing scheme improving the bitcell stability is developed. A specific read-assist circuit is also proposed in order to enable a large number of bitcells per column in a memory array. Finally, the designed bitcell offers up to 30% area gain compared to a planar six-transistor SRAM bitcell in the same technology node.

Process monitoring using automatic physical measurement based on electrical and physical variability analysis

A fully automated silicon-based methodology for systematic analysis of electrical features is shown. The system was developed for process monitoring and electrical variability reduction. A mapping step was created by dedicated structures such as static-random-access-memory (SRAM) array or standard cell library, or by using a simple design rule checking run-set. The resulting database was then used as an input for choosing locations for critical dimension scanning electron microscope images and for specific layout parameter extraction then was input to SPICE compact modeling simulation. Based on the experimental data, we identified two items that must be checked and monitored using the method described here: transistor’s sensitivity to the distance between the poly end cap and edge of active area (AA) due to AA rounding, and SRAM leakage due to a too close N-well to P-well. Based on this example, for process monitoring and variability analyses, we extensively used this method to analyze transistor gates having different shapes. In addition, analysis for a large area of high density standard cell library was done. Another set of monitoring focused on a high density SRAM array is also presented. These examples provided information on the poly and AA layers, using transistor parameters such as leakage current and drive current. We successfully define “robust” and “less-robust” transistor configurations included in the library and identified unsymmetrical transistors in the SRAM bit-cells. These data were compared to data extracted from the same devices at the end of the line. Another set of analyses was done to samples after Cu M1 etch. Process monitoring information on M1 enclosed contact was extracted based on contact resistance as a feedback. Guidelines for the optimal M1 space for different layout configurations were also extracted. All these data showed the successful in-field implementation of our methodology as a useful process monitoring method.