Static Power Research Articles

IMPACT OF SUPPLY VOLTAGE ON SRAM CELL POWER DISSIPATION UNDER DIFFERENT TOPOLOGIES

The high storage density and quick access times of Static Random Access Memory (SRAM) make it a critical component of many Very Large Scale Integration circuits. However, device scaling in today's technology leads to an increase in dynamic power and a decrease in noise margin, posing significant challenges to memory circuit design for the next generation of devices. In addition, sub-threshold leakage is also a concern. In recent years, the increasing demand for notebooks, laptops, IC memory cards, and mobile communication devices has driven the development of low-power, low-voltage memory circuits. Static Random Access Memoryis widely used as on-chip and off-chip memory for portable applications because they are easy to use and have minimal standby leakage. Since 60% to 70% of the chip memory is used, SRAM optimization is the focus of research. The SRAM cell's architecture and performance have been studied using various technologies to minimize power dissipation while maintaining stability. Based on the power dissipation, including static and dynamic power dissipation, and Static Noise Margin (SNM), the SRAM cell performance is compared with different topologies. The SNM fluctuation is considered along with the variation of supply voltage.

A Voltage-Assist 16-Channel Electrochemical Biosensor with Linearity Compensation.

Large capacitive loading of electrodes induces massive error current and imperfect settling in the electrochemical signal acquisition process, leading to inaccurate acquisition results. To efficiently mitigate this inaccuracy, this paper presents a current-and-voltage dual-mode acquisition technique in which a voltage front-end (VFE) is employed to acquire the electrode voltage error and compensate the nonlinearity induced by the electrode capacitive loading. Therefore, the gain and bandwidth requirements of the current front end (CFE) can be relaxed to reduce the complexity and power consumption. With a relieved gain requirement, an inverter-based capacitive trans-impedance amplifier (IB-CTIA) is adopted to boost the input transconductance for low-noise design. By reusing the supply current, the IB-CTIA effectively achieves a low input-referred current noise of 3.9 pArms and a dynamic range (DR) of 126 dB with only 18-μW static power. The prototype chip is fabricated in a 180-nm CMOS process. Interleukin-6 immunoassays (IL-6) are implemented to verify the chip's performance. With the proposed nonlinear error compensation, the correlation coefficient of the detection result is improved from 0.951 to 0.980 and the limit of detection (LoD) is reduced from 8.31 pg/mL to 6.90 pg/mL.

Beware Your Standard Cells! On Their Role in Static Power Side-Channel Attacks

Beware Your Standard Cells! On Their Role in Static Power Side-Channel Attacks

A Rail-To-Rail and Low Offset Novel Strongarm Comparator Circuit for Low Power Data Converter Architectures

With the rapid improvements in the design of advanced high performance communication receivers, hand-held electronic devices are in widespread usage for some time. These devices facilitate high speed and secured access to internet data. The demand for realizing a smart and better usage experience puts forth strict requirements on the design aspects of next-generation high speed low power complementary metal oxide semiconductor (CMOS) receiver design. One of the major modules in the implementation of high speed low power CMOS receiver device is the analog to digital converter (ADC) architecture. In the process of conversion from analog to digital signals, Quantization and sampling operations are vital and are realized using comparator circuits. The comparator design has a significant role in the design of data converter architecture. Several comparator architectures exist, but StrongARM topology is discussed and implemented in this work due to its negligible static power dissipation and rail to rail output voltages. The proposed novel comparator architecture is designed and simulated in 90nm CMOS process using Cadence Virtuoso tool and operated at supply voltage of VDD=1.5V, a clock frequency of 250MHz. Compared to the previous designs, the energy delay product was reduced by 8% which is an important observation to be observed for use in wireless sensor node applications.

An Open-Source Power System Simulation Toolchain for Teaching, Research, and Industrial Use

This paper describes a fully open-source toolchain for the modelling and simulation of phasor-based, balanced 3-phase AC system models, based on the OpenModelica compiler, the PowerGrids 2.0.0 Modelica library, and the open-source solvers IDA, Kinsol, and KLU. The toolchain includes a graphical user interface for model editing and result visualization. A notable feature is the automatic generation and solution of the initial static power flow, which provides good initial guess values for the steady-state initialization of the dynamic model, ensuring robust initialization; this feature can be disabled, and the results of external power flow tools can be used instead. The toolchain currently handles models with up to about 100 buses, making it attractive for teaching and research use, but is planned to be able to handle models with thousands of buses in the near future. This will be achieved thanks to new code generation features currently under development in OpenModelica and will open the way to industrial use.

The Disintegration of “Power/Knowledge”. Post-Socialist Studies as Decolonial Studies? A Personal Point of View. Part 3: Soft and Hard Variants of Post-Colonial Studies

The relationship between post-colonial and post-socialist studies is extraordinarily complex. Post-colonialists might argue that it can be approached from different perspectives as well as different power positions of knowledge production. As a result, I have chosen a specific trajectory that intersects and challenges the static power positions and is able to trace the debates and the unfolding of the complex problem over time. As a long-time scholar in this area, and moreover one who has taken many different roads in both fields, I will describe this relationship from the perspective of my own scholarly biography. However, my professional career has spanned several decades and surpassed the transient trends and fashions within this scholarly field. As such, it can only be depicted as an extensive narrative comprising multiple episodes, published in sequence across the double issue of the journal Studia Litteraria, devoted to forms of engagement in contemporary Southern and Western Slavic literatures. Part 3 discusses soft and hard variants of the complex “powers/knowledge”.

The Disintegration of “Power/Knowledge”: Post-Socialist Studies as Decolonial Studies? A Personal Point of View. Part 2: The Socialist Expansion of Post-Colonial Studies

The relationship between post-colonial and post-socialist studies is extraordinarily complex. Post-colonialists might argue that it can be approached from different perspectives as well as different power positions of knowledge production. As a result, I have chosen a specific trajectory that intersects and challenges the static power positions and is able to trace the debates and the unfolding of the complex problem over time. As a long-time scholar in this area, and moreover one who has taken many different roads in both fields, I will describe this relationship from the perspective of my own scholarly biography. However, my professional career has spanned several decades and surpassed the transient trends and fashions within this scholarly field. As such, it can only be depicted as an extensive narrative comprising multiple episodes, published in sequence across the double issue of the journal Studia Litteraria, devoted to forms of engagement in contemporary Southern and Western Slavic literatures. Part 2 focuses on the socialist expansion of Post-Colonial Studies.

Optimization of electrical properties and radio frequency applications of GeTe thin film

GeTe belongs to a chalcogenide phase change material, which can dynamically achieve reversible switching between the crystalline state of low resistivity and the amorphous state of high resistivity by utilizing the thermally induced phase change characteristics. The GeTe is an important functional material in the fields of memristors and nonvolatile radio frequency (RF) switches. For RF switch applications, this paper focuses on optimizing the electrical performance of GeTe thin films prepared by magnetron sputtering. By comprehensively analyzing the effects of substrate materials, sputtering conditions, and annealing conditions on the resistivity of crystalline GeTe films, effective conditions for preparing low resistivity GeTe films are explored. Fig. (a) shows that compared with the GeTe film on a SiO<sub>2</sub> substrate, the film on an Al<sub>2</sub>O<sub>3</sub> substrate can obtain higher crystallinity and lower resistivity. For the deposition power and pressure shown in Fig. (b), the combination of medium power (50–80 W) and low pressure (2–3 mTorr) is beneficial for low crystalline resistivity of GeTe film. Additionally, Fig. (c) shows that higher annealing temperature (350–400 ℃) can realize lower film resistivity. Finally, the experimental results show that the lowest crystalline resistivity of the prepared GeTe thin film reaches 3.6×10<sup>–6</sup> Ω·m, and the resistance ratio is more than 10<sup>6</sup>. Based on rectangular chips of GeTe film, a parallel millimeter-wave switch with zero static power is also constructed. As shown in Fig. (d), the insertion loss is less than 2.4 dB, and the isolation is greater than 19 dB in a 1–40 GHz frequency band, demonstrating the potential application of GeTe thin films in the field of broadband high-performance discrete nonvolatile RF switches.

Ultra-low power magneto-elastic analog-to-digital converter based on magnetic tunnel junctions and bicomponent multiferroic nanomagnet

<sec>In recent years, the utilization of artificial intelligence and big data has led to the rise of compute-in-memory signal processing as the primary method for ADC design. Spintronic memory devices, which have non-volatile and low static power consumption characteristics, are particularly suitable for the design of low-power, high-bandwidth compute-in-memory ADCs.</sec><sec>In this paper, a 3-bit magneto-elastic analog-to-digital converter (MEADC) is proposed, which comprises eight magnetic tunnel junctions (MTJs), where the MTJ free layer is a bicomponent multiferroic nanomagnet. The bicomponent multiferroic nanomagnet can attain deterministic magnetization switching under zero-field condition by regulating the strain-mediated voltage. It has been discovered that there is a linear correlation between the thickness of the piezoelectric layer and the critical flip voltage in a bicomponent multiferroic nanomagnet of a given size and material. Using this principle, the thickness of the piezoelectric layer is adjusted to allow the MEADC to have eight different voltage switching thresholds. This can make the analog signal converted into a combination of different magnetization states of eight multiferroic MTJ. A latch comparator and an independent read circuit are designed to detect the MTJ’s resistance state output a digital signal. Monte Carlo simulations indicate that the MEADC can achieve a 100% success rate of writing at room temperature. Additionally, the read circuit and write circuit are separated from each other, thus the same reference voltage can be set for each MTJ and result in higher readability. Micromagnetic simulation and numerical analysis demonstrate that the MEADC can operate at a maximum frequency of 250 MHz, and the energy consumption of a single conversion is only 20 aJ. Compared with the magnetic analog-to-digital converter based on the Racetrack technology, the energy consumption is reduced by 1000 times, and the sampling rate is increased by 10 times. The MEADC proposed in this paper offers an essential technical support for the spintronics-based compute-in-memory integrated circuit architecture.</sec>

The Disintegration of “Power/Knowledge”: Post-Socialist Studies as Decolonial Studies? A Personal Point of View. Part 1: Post-Colonialism, Balkanism and Self-Colonization

The relationship between post-colonial and post-socialist studies is extraordinarily complex. Post-colonialists might argue that it can be approached from different perspectives as well as different power positions of knowledge production. As a result, I have chosen a specific trajectory that intersects and challenges the static power positions and is able to trace the debates and the unfolding of the complex problem over time. As a long-time scholar in this area, and moreover, one who has taken many different roads in both fields, I will describe this relationship from the perspective of my own scholarly biography. However, my professional career has spanned several decades and surpassed the transient trends and fashions within this scholarly field. As such, it can only be depicted as an extensive narrative comprising multiple episodes. Each episode showcases its unique scientific intrigue and unravels its own methodological peripeteia, all of which contribute to the overarching story I wish to share. Such complex material required a specific structure and organization, leading to the formation of three distinct parts of the story. These parts are published in sequence across the double issue of the journal Studia Litteraria, devoted to forms of engagement in contemporary Southern and Western Slavic literatures.

New, Fast, High-Performance Level Shifter for Buck DC-DC Converter in 180nm CMOS Technology

To reduce power dissipation, the dual supply voltage approach is required for analog circuits in the on-chip integrated circuits. In this paper, a novel circuit of the level shifter for Buck DC-DC Converter using cross-coupled configuration is presented. The proposed work of this paper uses this level shifter to converter voltage of 1.8V to 5V at 180 nm CMOS Technology in Cadence Virtuoso Tool. The propagation delay, energy/transition, and static power were 182.42pS, 0.01 fJ/Transition, and 6 fW, respectively. The final design area is only 60.142 μm2.

The Charging and Discharging of Reverse Biased Schottky Diode Voltage-Dependent Capacitor


 Transient analysis of RC circuit with voltage step source, constant resistor and nonlinear voltage-dependent capacitors with the capacitance given by C(vc) = Co/√(1+vc/Vbi), where Co and Vbi are constant and vc is the voltage across the capacitor, was carried out. The analysis was restricted to this class of nonlinear capacitors, because they represent with acceptable approximation the capacitances of reverse-biased Schottky diodes, which are very important and usually used in several static power converters practical applications. The charging and discharging are described by explicitly solvable nonlinear first-order differential equations. The theoretical analysis results are verified by numerical examples with computer simulation and also by experimentation in the laboratory.
 

Source of IC power consumption and low power design

In these years, with the continuous development of 14nm and 7nm chip processes and the increasing popularity of computers, cell phones, and smart homes, the growing market of electronic products and ultra-fine research for the reliability of the chip requirements gradually increased. The method of reducing power consumption in the new context of new technology is called the chip field die-cut concern. This paper mainly summarizes two aspects of power consumption sources and methods to reduce power consumption, to provide a reference basis for future research directions: First, the major sources of power consumption are static power consumption and dynamic power consumption. The primary sources of static power consumption are sub-threshold leakage and gate leakage current. This paper also mentions some other leakage currents, such as reverse bias PN junction current and induced leakage current, which can be more carefully considered when exploring methods to reduce power consumption. A more comprehensive consideration when exploring ways to reduce power consumption. Dynamic power consumption is mainly divided into Switching power and Internal power and short-circuit power. Then we summarize the existing methods which can reduce power consumption: Clock gating (including Clock gating without a latch and Clock gating with a latch), Dynamic voltage and frequency scaling, multi-supply and multi-voltage technology, Power gating and multi-threshold voltage. These methods are from a proprietary perspective to reduce power consumption.

Multiple Grid-Connected Microgrids with Distributed Generators Energy Sources Voltage Control in Radial Distribution Network Using ANFIS to Enhance Energy Management

Voltage conditions and power quality for customers and utility equipment are significantly impacted by the addition of microgrid-generating sources within distribution networks. Designing the right control for distributed generators for the various generating units of a Microgrid is important in enabling the synchronization of renewable energy generation sources, energy storage unity, and integration of Microgrids into a radial distribution network. This research provides control mechanisms based on an adaptive technique employing ANFIS, to reduce fluctuation of voltage and current difficulties faced when multiple renewable energy sources and storage systems are incorporated into a distribution network. A step-by-step Voltage Source Converter (VSC) Controller was designed for controlling the DC voltage power sources used. The ANFIS training, test system modeling, and the distributed energy source were modeled in MATLAB/SIMULINK 2021a Software. Four microgrids were developed each consisting of a Photovoltaic plant, Wind Turbine, and Battery Storage System. Non-critical and critical loads were considered during the system testing. The simulated result reveals that the proposed control system works effectively in maintaining a constant system voltage of 340VAC which significantly mitigates system voltage and current fluctuation without using any static synchronous compensator (STATCOM) and power system stabilizers.

Research on the application of inertially stabilized platform in the dynamic measurement of cold atomic gravimeter

Dynamic gravity field measurement based on the cold atom absolute gravity measurement system has important applications in geological exploration, gravity field mapping and other fields. The inertial stabilized platform is the key component of the dynamic cold atom absolute gravity measurement system, which can isolate the interference of carrier angle motion and keep the atomic gravimeter probe in the horizontal attitude during the measurement process. In this paper, according to the dynamic measurement requirements of atomic gravimeter, a high-precision two-axis inertial stabilized platform system is designed. The relationship between attitude angle and gravity measurement error is analyzed, and the stability of the system is enhanced by lead-lag method. Then the static vertical vibration power spectrum of the platform is measured to consider its influence on dynamic gravity measurement. Finally, a dynamic gravity test experiment was conducted in the Yellow Sea to verify the attitude control accuracy of the platform, and the attitude data of the platform under different heading were evaluated. The attitude standard deviation of the platform was better than 4 × 10−5 rad, and the absolute gravity standard deviation of the linear round-trip measurement reached 1.49 mGal. The experimental data show that the inertial stabilized platform can meet the dynamic measurement requirements of the cold atom gravimeter.

Dynamic alpha power modulations and slow negative potentials track natural shifts of spatio-temporal attention.

Alpha power modulations and slow negative potentials have previously been associated with anticipatory processes in spatial and temporal top-down attention. In typical experimental designs, however, neural responses triggered by transient stimulus onsets can interfere with attention-driven activity patterns and our interpretation of such. Here, we investigated these signatures of spatio-temporal attention in a dynamic paradigm free from potentially confounding stimulus-driven activity using electroencephalography. Participants attended the cued side of a bilateral stimulus rotation and mentally counted how often one of two remembered sample orientations (i.e., the target) was displayed while ignoring the uncued side and non-target orientation. Afterwards, participants performed a delayed match-to-sample task, in which they indicated if the orientation of a probe stimulus matched the corresponding sample orientation (previously target or non-target). We observed dynamic alpha power reductions and slow negative waves around task-relevant points in space and time (i.e., onset of the target orientation in the cued hemifield) over posterior electrodes contralateral to the locus of attention. In contrast to static alpha power lateralization, these dynamic signatures correlated with subsequent memory performance (primarily detriments for matching probes of the non-target orientation), suggesting a preferential allocation of attention to task-relevant locations and time points at the expense of reduced resources and impaired performance for information outside the current focus of attention. Our findings suggest that humans can naturally and dynamically focus their attention at relevant points in space and time and that such spatio-temporal attention shifts can be reflected by dynamic alpha power modulations and slow negative potentials.

A Review of Recent Control Trchniques of Virtual Synchronous Machine for Renewable Energy

Abstract Increased distributed generation (DG) integration into power system via power electronic devices results in a reduction in the total equivalent inertia of power grid utility, which lead to serve frequency stability and performance degradation of the power system. To facilitate the penetration of DG into the power grid utility, improved control schemes of the power electronics converter based DG are required to improve the system stability when it is dominated by DG based inverter. A virtual synchronous generator (VSG ) approach is suggested, which consists in controlling the static power converter to mimic the essential dynamic behavior of the conventional synchronous generator. The main objective of this paper is to review the most recent topologies of virtual inertia control. Along this work, a detail description of each topology is presented. In addition, VSG control equations given voltage and frequency control is explained in detail. The VSG problems and future research on VSG control are discussed.

Transient Stability Impact of Short Circuit Fault System Based on SVC And PSS Applications

Researchers are currently focusing on two solutions, namely Static VAR compensator (SVC) and power system stabilizer (PSS), to address different power system stability issues in large area interconnected power grids. To enhance transient stability, researchers have suggested a combined approach involving SVC and PSS. In this method, SVC and PSS coordinate and cooperate with each other to provide better stability assurance. To verify the feasibility of this method, simulation experiments were conducted using MATLAB. Simulated the situation of single-phase ground fault, two-phase ground fault, and three-phase ground fault in the power system, and tested the effectiveness of SVC and PSS respectively. The simulation results show that the combined use of SVC and PSS can significantly improve the transient stability of power systems and effectively reduce the impact of faults on the system. In summary, the combined use of SVC and PSS can effectively solve various power system stability issues that may arise in large-scale interconnected power grids. By conducting simulation experiments in MATLAB, researchers have verified the feasibility of this method under different fault conditions, providing strong support for practical applications.

Application Specific Reconfigurable Processor for Eyeblink Detection from Dual-Channel EOG Signal

The electrooculogram (EOG) is one of the most significant signals carrying eye movement information, such as blinks and saccades. There are many human–computer interface (HCI) applications based on eye blinks. For example, the detection of eye blinks can be useful for paralyzed people in controlling wheelchairs. Eye blink features from EOG signals can be useful in drowsiness detection. In some applications of electroencephalograms (EEGs), eye blinks are considered noise. The accurate detection of eye blinks can help achieve denoised EEG signals. In this paper, we aimed to design an application-specific reconfigurable binary EOG signal processor to classify blinks and saccades. This work used dual-channel EOG signals containing horizontal and vertical EOG signals. At first, the EOG signals were preprocessed, and then, by extracting only two features, the root mean square (RMS) and standard deviation (STD), blink and saccades were classified. In the classification stage, 97.5% accuracy was obtained using a support vector machine (SVM) at the simulation level. Further, we implemented the system on Xilinx Zynq-7000 FPGAs by hardware/software co-design. The processing was entirely carried out using a hybrid serial–parallel technique for low-power hardware optimization. The overall hardware accuracy for detecting blinks was 95%. The on-chip power consumption for this design was 0.8 watts, whereas the dynamic power was 0.684 watts (86%), and the static power was 0.116 watts (14%).

Tunable optical power splitter based on directional coupler structure with phase change material Sb2Se3

Traditional optical power splitters (OPSs) have fixed power split ratios, and although some can be tuned with an electro-optic polymer, continuous energy supply increases power consumption. Combining OPS with chalcogenide phase-change materials (PCMs) allows us to tune the power split ratio with a low power owing to the nonvolatility and contrasting optical properties of the PCM. In this paper, a compact 1 × 2 arbitrary ratio OPS with hybrid directional coupler structure with PCM Sb2Se3 is proposed for lower-power and reconfigurable PICs. It demonstrates a continuous change in the power split ratios by changing the crystalline fraction of the Sb2Se3 material covered on coupling waveguide. The non-volatile states of Sb2Se3 enables zero static power of the device. The splitting ratio can be tuned in a broad range from 1 % to 97 % with the excess loss of 0.11 dB at 1550 nm. Such device can be extended to perform a handwritten digit recognition task with the simulated properties to determine the performance of the OPS device in the neuromorphic network. Its recognition accuracy achieves as high as 95 % for the MNIST (Modified National Institute of Standard and Technology) handwritten digits, which is close to that of device with ideal characteristics based on the software computing. The results indicate that the proposed OPS can not only achieve large range tunable power allocation, but also be further applied to large-scale PICs and optical neuromorphic networks.