Static Power Research Articles

Design and Optimization of 4-Bit Array Multiplier with Adiabatic Logic Using 65 nm CMOS Technologies

ABSTRACT This paper proposes a 4-bit array multiplier useful in the design of basically mixer circuit, which is highly involved in signal and image processing using an efficient low-power VLSI technique. The presented architecture is completely implemented adiabatic techniques in the Near Threshold Region, which optimize the product of propagation delay and power dissipation. Multiplier is the most frequently used element in many digital electronics applications. Depending on the applications, various types of multipliers emerge. With this technique, the total power dissipation, i.e. dynamic power dissipation as well as static power dissipation is less as compared to the conventional CMOS technique. The Near Threshold Adiabatic Logic (NTAL) technique is used with a single timevarying power supply which reduces the clock tree management and enhances the energy-saving capability. Simulation of the proposed design is done by Cadence virtuoso schematic editor with specter simulator on TSMC 65 nm technology node to verify the optimized result. Also comparing our result to conventional CMOS techniques with all the same design parameters, the result shows that power dissipation improvement of approximately 66.6%, 14.4%, and 64.6% with respect to varying frequency, supply voltage, and load capacitance with other parameters keep constant such as if the frequency is varying than capacitance load value is C load = 10 pF and V DD(max) = 1.2 V, similarly if the supply voltage is varying than capacitance load value is C load = 10 pF and frequency F = 4 GHz and if load capacitance is varying than frequency F = 4 GHz and supply voltage V DD(max) = 1.2 V.

Miniaturized Wirelessly Powered and Controlled Implants for Multisite Stimulation.

This paper presents a miniaturized implant with a diameter of only 14 mm, which houses a novel System on Chip (SoC) enabling two voltage level stimulation of up to 16 implants using a single Tx coil. Each implant can operate at a distance of 80 mm in the air through the inductive resonant link. The SoC consumes only 27 μW static power and enables two channels with stimulation amplitudes of 1.8 V and 3.3 V and timing resolution of 100 μs. The SoC is implemented in the standard 180 nm complementary metal oxide semiconductor (CMOS) technology and has an area of 0.75 mm × 1.6 mm. The SoC comprises an RF rectifier, low drop-out regulator (LDO), error detection block, clock data recovery, finite state machine (FSM), and output stage. Each implant has a PCB-defined passcode, which enables the individual addressability of the implants for synchronized therapies. The implantable device weighs only 80 mg and sizes 20.1 mm3. Tolerance of up to 70° to angular misalignment was measured at a distance of 50 mm. The efficacy of bilateral stimulation was further verified by implanting two devices on two sides of a pig's neck and performing bilateral vagus nerve stimulation (VNS), while monitoring the heart rate.

A 17.6-Bit 800-SPS Energy-Efficient Read-Out IC With Input Impedance Boosting

A 17.6-bit, 800-sample-per-second (SPS) read-out integrated circuit has been implemented for a bridge sensor. The read-out integrated circuit has a capacitively-coupled instrumentation amplifier (CCIA) with a sensor offset voltage compensation circuit, an amplifier offset voltage compensation circuit, and an input impedance boosting loop (IBL). Followed by the CCIA, a programmable-gain third-order discrete-time incremental delta-sigma (ΔΣ) analog-to-digital converter (ADC) with an output data-rate of 12.8 kHz shortens the sensing time to reduce the static power consumption of the resistive bridge sensor and the read-out IC. To boost the input impedance of the CCIA, the system-level input and output choppers operate at a frequency of 12.8 kHz. The ΔΣ modulator converts the modulated signal to digital with a sampling clock of 4 MHz. The system-level chopping reduces the residual offset and the low-frequency noise with an on-chip cascade of integrators (CoI) filter. Implemented in a 0.13 μm CMOS process, the read-out circuit achieves an input impedance of 22 MΩ at a data-rate of 800 SPS, a sensor offset compensation range of ± 350 mV, a maximum effective resolution of 17.6 bits, and an input-referred noise of 1.72 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</sub> at a gain of 128. It draws an average current of 106.3 μA from a 3 V supply and 1.3 μA from a 1.5 V supply.

Scalable and ultralow power silicon photonic two-dimensional phased array

Photonic integrated circuit based optical phased arrays (PIC-OPAs) are emerging as promising programmable processors and spatial light modulators, combining the best of planar and free-space optics. Their implementation on silicon photonic platforms has been especially fruitful. Despite much progress in this field, demonstrating steerable two-dimensional (2D) OPAs that are scalable to a large number of array elements and operate with a single wavelength has proven a challenge. In addition, the phase shifters used in the array for programming the far-field beam are either power hungry or have a large footprint, preventing the implementation of large scale 2D arrays. Here, we demonstrate a two-dimensional silicon photonic phased array with high-speed (∼330 kHz) and ultralow power microresonator phase-shifters with a compact radius (∼3 µm) and 2π phase shift ability. Each phase-shifter consumes an average of ∼250 µW of static power for resonance alignment and ∼50 µW of power for far-field beamforming, a more than one order of magnitude improvement compared to prior OPA works based on waveguide-based thermo-optic phase shifters. Such PIC-OPA devices can enable a new generation of compact and scalable low power processors and sensors.

Design of Full Swing Carry Generator Using Mentor Graphics

Abstract: A Full adder is built specifically for creating full-swing carry output utilizing Mentor graphics in this project. Mentor Graphics is electronic design automation software that is used to create superior electronic devices more quickly and costeffectively. The proposed circuit, which has a high driving capability, is suitable for a wide range of multistage structure applications. In digital processing equipment, full adders are used for multiple adders. This circuit design employs a unique mode to provide a full swing carry output, and its performance is governed by suitable inputs, static power reduction, and transistor series construction. The full adder proposed here is an efficient gate for Integrated Circuits (ICs). The performance between simulation and measurement produced a very good approximation result. When compared to other circuits, the cell's performance under variations indicates its excellent driving capabilities while consuming very little power and PDP. The circuit makes use of a one-of-a-kind module to provide full-swing Carry output, and its performance is governed by appropriate inputs, static power reduction, and transistor series formations.

Power analysis of thyristor-regulated reactor with fully controlled semiconductor valves

Flexible AC transmission systems that are built by using modern advances in power electronics are key components of smart grids. The object of research is a thyristor-controlled reactor, which is used as part of a static reactive power compensator to control the reactive power in the transmission and distribution electrical networks of power supply systems. It is proposed to use two-operation semiconductor gates in the regulator, which made it possible to obtain qualitatively new adjusting properties. The analysis of reactor power under the mode of phase control of the conductive state of gates by setting the moments of their closing time was carried out. Analytical expressions for angular power characteristics of the main harmonic were derived. It was revealed that by regulating, based on the phase principle, the conductive state of ideal semiconductor gates, which are switched on in series with ideal inductance, along with the adjustment of reactive power, the phenomenon of consumption of active power from the grid at the main harmonic is observed. It is shown that the reason for this is artificially obtained, with the help of semiconductor gates, active-inductive nature of the angle of displacement of the main harmonic of the current in the reactor relative to the voltage of the power supply. The study results prove the effect of adjusting the active power by a thyristor-regulated reactor. Research involving a virtual model illustrated the adjustment of the active power component of a synchronous generator by the effect on the rotor speed during gate adjustment of reactor power. The active power resource obtained in the process of thyristor adjustment of the reactor is commensurate with its installed capacity

A novel CNTFET based Schmitt-Trigger read decoupled 12T SRAM cell with high speed, low power, and high [formula omitted]/[formula omitted] ratio

Many researchers are working to develop a static random access memory (SRAM) cell that uses low power, has good stability, better Ion/Ioff ratio and speed. This paper presents a single sided Schmitt-trigger driven read decoupled 12 transistors (STRD 12T) carbon nanotube field-effect transistor (CNTFET) SRAM cell with controlled power gating approach. The Schmitt-trigger (ST) inverter along with power gating and read decouple approach has low power, good read and write delay, better stability and Ion/Ioff ratio. The stacking effect reduces the leakage power of the proposed cell. The proposed STRD 12T SRAM illustrates the maximum reduction in static power consumption, write delay, read delay, and maximum improvement in Ion/Ioff ratio is 1544.34, 112.37, 1.40, and 8107.88 times respectively, than the considered SRAM cells. The simulation is performed with Cadence Virtuoso utilizing the 32 nm CNTFET model from Stanford University.

A highly stable and low‐cost 12T radiation hardened SRAM cell design for aerospace application

SummaryIn this paper, a highly stable and low‐cost 12T (HSLC12T) radiation hardened static‐random‐access‐memories (SRAM) cell is proposed in 55 nm CMOS technology. Based on polarity reversal design and read/write separation structure, the proposed HSLC12T cell can recover from any single event upsets (SEUs) induced at all its sensitive nodes and even single event double‐node‐upsets (SEDNUs) induced at its internal storage node pair Q‐QN, while also having the maximum read static noise margin (RSNM) and lower static hold power, as well as excellent write speed and write‐ability. Though the HSLC12T cell exhibits a larger read delay, it has the best overall performance of all other cells. This is proven by having the highest electrical quality metric (EQM) value, thus making the proposed HSLC12T cell a better choice for aerospace applications.

An Equal Precision Programmed Cymometer Design Using Low-Power Technique

Based on equal precision frequency measurement and pulse counting technique, a multi-period synchronous frequency measurement method is proposed in this paper. A programmed cymometer is designed with a full frequency band with equal precision measurement and improved measurement accuracy. In addition to adopting a low-power gate-control clock technique, the strong stability of our design is also carried out through the filtering of interference signals. Finally, the designed circuit is implemented with FPGA. The experimental results show that the static power consumption of the programmable frequency meter testing platform designed after continuous operation for 100 h is only 0.56 W, and the input impedance is 1 M Ω/40 pF. At the same time, the errors of frequency, cycle measurement, duty cycle measurement, and time interval are within a reasonable range. In addition, the measurement accuracy requirements for various indicators can also be met at a maximum frequency of 100 MHz. Therefore, this work can provide a feasible design method for low-power consumption electrical systems that are easy to replicate.

Reconfigurable Field‐Effect Transistor Technology via Heterogeneous Integration of SiGe with Crystalline Al Contacts

AbstractReconfigurable field‐effect transistors, capable of being dynamically programmed during run‐time, overcome the static nature of conventional complementary metal‐oxide semiconductors by reducing the transistor count and the circuit path delay. Thereby, SiGe and Ge are predicted to boost drive currents, switching speed and to reduce power consumption. Nevertheless, Ge‐based reconfigurable field‐effect transistor prototypes have so far fallen short in reaching both the promised performance due to interface instability to their contacts and gate oxides, as well as in reaching the current–voltage symmetry necessary for circuit applicability. Here, a top‐down fabricated SiGe‐based reconfigurable transistor technology is reported that is comprised of a vertical Si‐Si0.67Ge0.33 heterostructure enabling the envisioned high and symmetric on‐currents of both n‐ and p‐type operation. Monolithic integration with single‐elementary crystalline Al contacts alleviates process variability compared to conventional Ni‐silicide/Ni‐germanide contacts and introduces an ultra‐thin Si interlayer providing stability and equal injection efficiency of holes and electrons. The implementation of a three top‐gate transistor in combination with a hysteresis‐free Si/SiO2/HfO2 gate stack enhances polarity control and leakage current suppression to limit static power dissipation. Importantly, the obtained Al‐Si‐SiGe multi‐heterojunction and advanced reconfigurable transistor design is the first Ge‐based technology showing the envisioned stability and performance enhancements.

A perspective on the doping of transition metal dichalcogenides for ultra-scaled transistors: Challenges and opportunities

To support the ever-growing demand for faster, energy-efficient computation, more aggressive scaling of the transistor is required. Two-dimensional (2D) transition metal dichalcogenides (TMDs), with their ultra-thin body, excellent electrostatic gate control, and absence of surface dangling bonds, allow for extreme scaling of the channel region without compromising the mobility. New device geometries, such as stacked nanosheets with multiple parallel channels for carrier flow, can facilitate higher drive currents to enable ultra-fast switches, and TMDs are an ideal candidate for that type of next generation front-end-of-line field effect transistor (FET). TMDs are also promising for monolithic 3D (M3D) integrated back-end-of-line FETs due to their ability to be grown at low temperature and with less regard to lattice matching through van der Waals (vdW) epitaxy. To achieve TMD FETs with superior performance, two important challenges must be addressed: (1) complementary n- and p-type FETs with small and reliable threshold voltages are required for the reduction of dynamic and static power consumption per logic operation, and (2) contact resistance must be reduced significantly. We present here the underlying strengths and weaknesses of the wide variety of methods under investigation to provide scalable, stable, and controllable doping. It is our Perspective that of all the available doping methods, substitutional doping offers the ultimate solution for TMD-based transistors.

Integrated Low‐Dimensional Semiconductors for Scalable Low‐power CMOS Logic

AbstractScalable nanoelectronics with energy‐efficient logic technology is crucial for next‐generation edge devices. Low‐dimensional semiconductors, such as transition metal dichalcogenides and single‐walled carbon nanotubes (SWCNTs), have tunable properties with reduced short‐channel effects. The unique properties of each material can be utilized owing to the heterogeneous integration of multiple semiconducting channels to form complementary metal‐oxide‐semiconductor (CMOS) logic. However, the integration remains challenging. This study reveals the realization of low static power hetero‐CMOS inverters by the integration of n‐type monolayer MoS2 and p‐type SWCNT networks. The balanced inverter exhibits a large peak gain of ≈67 at a supply voltage of 2 V with the customized design of the wafer‐scale synthetic process and channel integration. An ultralow standby power consumption of ≈5 pW and a practical peak gain of ≈7 at a reduced supply voltage of 0.25 V are achieved. A high noise margin (&gt;70%) validates the circuit's tolerance to external noises and the dynamic analysis of the inverting amplifier in push–pull configuration exhibits a large AC gain. This work paves the way toward the wafer‐scale integration of low‐dimensional materials for low‐power nanoelectronics.

Quasi-static Power Flow and Fault Analysis of Photovoltaic Farm

This report first analysis quasi static power flow for photovoltaic power plant. Then, fault analysis for different symmetrical and asymmetrical fault is done. The system used is IEEE 39 bus New England system that a Photovoltaic farm with 500 MW power is connected to bus 24. Newton-Raphson Power flow method is used with Gauss-Jordan elimination method for matrix inversion in this power flow analysis. Different operation condition including faults are also considered for fault at bus 16. The results are validated with simulation in MATLAB software.

An adaptive link training based hybrid circuit topology for full‐duplex on‐chip interconnects

SummaryThis work proposes a link training based half‐rate dynamic current‐steering echo‐cancellation hybrid circuit topology for full‐duplex signaling that performs echo cancellation by deploying a bit error detection unit and backchannel adaptation. In addition, this work proposes a power‐efficient half‐rate dynamic current‐steering logic hybrid circuit for full‐duplex signaling over on‐chip interconnects for simultaneous transmission and reception. The half‐rate dynamic current‐steering hybrid circuit topology has low static power consumption compared with traditional current‐mode circuit topology implementations, thanks to the discrete nature of the current‐steering hybrid topology. The proposed scheme is implemented in 1.2 V, 65‐nm complementary metal‐oxide semiconductor (CMOS). The performance results show that the link training scheme sets the control bits for both the transmitter driver and hybrid circuit topology when the backchannel adaptation loop gets locked for 1‐ and 3‐mm interconnects for process, voltage, and temperature (PVT) variations. The proposed hybrid circuit topology is able to receive the required far‐end transmitted data with the link training scheme and has the differential recovered received signal voltage swing of 1.2 V for both 1‐ and 3‐mm interconnect at the 10‐Gb/s data rate. The total power consumption of the hybrid is 3 and 3.5 mW for 1‐ and 3‐mm interconnect with an energy efficiency of 0.6 and 0.7 pJ/bit, respectively, at 10‐Gb/s full‐duplex operation.

A Static and Dynamic Analysis of Photovoltaic Penetration into MV Distribution Network

Photovoltaic (PV) systems are becoming increasingly prevalent worldwide, particularly in power distribution networks. However, their intermittency and integration into distribution networks can have adverse effects. This study investigates the impact of large-scale solar integration into a typical Malaysian power grid network, focusing on voltage stability, short circuits, and power loss under peak and no-load conditions. Using Digsilent Power Factory software, static and dynamic power flow analyses were performed on a network consisting of two 132/11 kV transformers, an 11 kV busbar, and 112 loads served through eight feeders. Solar PV of 100 kW was integrated into each node, and the maximum allowable solar grid connection level was determined. The static results show that there were no violations in no-load conditions at 100 kW PV penetration. However, during peak load, there were violations at 0% PV penetration, but by increasing the level of solar grid connection to 60% (60 kW), the voltage level moves up to the acceptable range. Under contingency conditions, the results show that the minimum level of solar penetration is 80% (80 kW). The highest power loss occurs during peak time and is observed at 0% PV penetration. Feeder 8, the lounge feeder with the highest number of loads, is identified as the main cause of power loss. According to the short circuit analysis in peak and no-load conditions, the system experiences the highest shorts during peak loads. On the other hand, we conducted a dynamic simulation with load characteristics and compared the results for different levels of PV penetration. The results from the dynamic simulations show that lower limit violations occur even at 100% PV penetration for a brief period in all case studies. This study identifies the maximum permissible PV penetration as 125 kW.

Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains

To effectively minimize static power for a wide range of applications, power domains for coarse-grained reconfigurable array (CGRA) architectures need to be more fine-grained than those found in a typical application-specific integrated circuit. However, the special isolation logic needed to ensure electrical protection between off and on domains makes fine-grained power domains area- and timing-inefficient. We propose a novel design of the CGRA routing fabric that reduces the area overhead of power domain boundary protection from around 9% to less than 1% without incurring any extra timing delay from the isolation cells. Conventional Unified Power Format based flow for power domain boundary protection does not support this design choice. Therefore, we create our own compiler-like passes that iteratively introduce the needed design changes, and formally verify the transformations using methods based on satisfiability modulo theories. These passes also let us optimize how we handle test and debug signals through the off tiles in the CGRA. Using our framework, we add power domains to a CGRA that we designed and taped out. The CGRA has 32 × 16 processing element and memory tiles and 4-MB secondary memory. We address the implementation challenges encountered due to the introduction of fine-grained power domains, including the addressing of the CGRA tiles, the power grid design, well substrate connections, and distribution of global signals. Our CGRA achieves up to 83% reduction in leakage power and 26% reduction in total power versus an identical CGRA without multiple power domains, for a range of image processing and machine learning applications.

Inversion-Type Ferroelectric Capacitive Memory and Its 1-Kbit Crossbar Array

By modulating the capacitance to store data, ferroelectric capacitive memories (FCMs) show distinct advantages compared with the conventional resistive memories, including the near-zero static power, negligible read disturbance, and immunity to IR drop problem. However, the promise of FCMs requires the improvement of their electrical characteristics, including retention, capacitance ratio, and operation speed. In this work, by introducing a heavily doped region in the metal–ferroelectric–semiconductor (MFS) structure, we propose and experimentally demonstrate an inversion-type FCM device, which simultaneously achieves: 1) high ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 125$ </tex-math></inline-formula> ) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {HCS}}/{C}_{\text {LCS}}$ </tex-math></inline-formula> ratio; 2) ten-year retention under 85 °C; 3) multistate operation; and 4) improved write speed in nanosecond range. Integrating the devices on Silicon on insulator (SOI) substrates, we also realize the 1-kbit inversion-type FCM crossbar array. By setting up a test platform with a specially designed drive circuit, the read/write operation of the capacitive array is successfully demonstrated, evidencing the stable operation of the capacitive memory device in the array level.

Impedance Modeling and Mechanism Analysis of Low-Frequency Oscillations in Single-Phase MMC-RPC Integrated Vehicle-Grid Coupling System

The single-phase modular multilevel converter-based railway static power conditioner (MMC-RPC) has significant advantages in governing the power quality problems in the traction power supply system. The mechanism analysis of low-frequency oscillations (LFOs) in the MMC-RPC integrated vehicle-grid coupling system when electric multiple units are put into operation is a critical issue, which has been investigated in this article. The third-order ac admittance models of single-phase MMC-RPC and vehicle rectifiers are developed for the first time. To comprehensively study the small-signal stability of the MMC-RPC integrated vehicle-grid coupling system, this article proposes a modal analysis method based on modal phase margin and parameter sensitivity and combined with the generalized Nyquist stability criterion. It is found that LFOs around 10 Hz or 48 Hz are prone to occur due to the interactions of MMC-RPC or vehicle rectifiers with the traction power grid. To reveal the LFO mechanism, dominant modes and key parameters leading to LFOs in different working scenarios are clarified, and a series of guidelines are proposed for LFO elimination. Furthermore, the effects of control loops and power flow of MMC-RPC on system stability are revealed in detail. Finally, real-time hardware-in-the-loop experimental results validate the theoretical analysis.

Кремниевый с полностью охватывающим затвором полевой нанотранзистор с нелинейной геометрией рабочей области

A silicon CMOS nanotransistor with a cylindrical geometry with a fully enclosing gate with a non-linear geometry of the working area is discussed. Numerical studies of prototypes with a parabolic working area were performed using mathematical modeling using the software environment for instrumental technological modeling TCAD, based on the models of n- and p-type nanotransistors developed by TCAD. An inverter model has been developed for n- and p-type prototypes with an optimized radius ratio of 0.76. At control voltages of 0.6 V and a frequency of 25 GHz, the model predicts a maximum switching delay of 1.0 ps, an active power limit of 0.22 µW, and a static power of 72 pW. The electrophysical characteristics of the n-type prototype with dielectric stacks of gate oxide SiO2-Al2O3 and SiO2-HfO2 are analyzed numerically. The simulation results show that the use of high k stacks has a noticeable effect on key transistor characteristics. Thus, a parabolic nanotransistor architecture with an optimized radius ratio can potentially become a replacement for a cylindrical structure for high-speed low-voltage applications.

Single Tuned Filter Design for Mitigating Harmonic Distortion in (30 KV) ALTAHRER Substation

Nowadays, due to the fast growth of electronic devices, harmonic issues have become a main matter for current day electrical operators. Some of the causes of harmonics are: a) ripples in voltage waveform of machines, b) flux distortion in the synchronous machines, c) transformer magnetizing currents, d) non-linear loads such as static power converters, arc furnaces, and e) static-var compensators as suppliers of continuously variable var sources. The harmonic filtering is one of the solutions for preventing the worrying harmonics from entering the rest of the system. There are basically two types of filters: i) passive, where the filter components are passive elements such as resistor, inductor, and capacitor, and ii) active, where the filter has a controlled current or voltage source. This peper introduces a single-tuned passive filter to minimize the harmonic distortion of AL-TAHRER substation (30KV). The offered filter and studied system modeling are built by ETAP software. Results show the effectiveness of the proposed filter in mitigating total harmonic distortion of studied system