Static Power Research Articles

Distributed photovoltaic reactive power control strategy based on improved multiobjective particle swarm algorithm

AbstractDistributed power supply access to the distribution network, although it can effectively support the band voltage, will also cause problems such as voltage overruns at the point of grid connection and large network losses, so this paper establishes a reactive power optimization model containing three objectives: network loss, voltage fluctuation rate, and static reactive power generator (SVG) installation capacity in distributed photovoltaic power generation scenarios by taking advantage of the characteristics of SVG that both absorb and send out reactive power. A multiobjective particle swarm algorithm with an adaptive grid and roulette mechanism is introduced to ensure the uniformity and diversity of the Pareto boundaries under the constraint that the output of each device does not exceed the constraints, and to obtain the optimal set of solutions capable of coping with the stochastic fluctuations of distributed power sources. When the algorithm is compared with three other algorithms, such as nondominated sorting genetic algorithm‐II, the results show that it reduces the network loss by about 25% and significantly improves the voltage fluctuation rate.

Static and dynamic power splitting protocol enabled in DF energy harvesting Half-Duplex relaying network: Ergodic capacity analysis

In this research, we propose and examine the DF Energy Harvesting Half-Duplex Relaying Network. For this system model, the DF Energy Harvesting Half-Duplex Relaying Network is analyzed in two cases: Static and Dynamic Power Splitting Protocol. The Ergodic Capacity (EC) is introduced and derived in relation to all the primary system parameters in order to evaluate system performance. The Monte Carlo simulation results demonstrate that the mathematical and simulation are in agreement, thereby confirming the accuracy of the analytical description.

Drain self-blocking ambipolar transistors for complementary circuit applications

The development of complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) based on two-dimensional (2D) materials offers an important opportunity to reduce static power and increase the integration density of integrated circuits. One promising approach to realize these CMOSFETs is to employ ambipolar 2D materials as channel materials with designed device structure to control the carrier transport properties for CMOSFET characteristics. However, these devices always suffer from complex multi-gate electrode structure, and hence face challenges in complicated inter-connection design and excessive voltage source requirement for circuit implementation. Here, we develop a three-terminal CMOSFET using ambipolar 2D material based on the drain electric field-induced carrier injection self-blocking mechanism. The designed drain electrode can effectively suppress carrier injection from the drain to the channel material, while the gate voltage can only regulate carrier injection in the source region. As a result, we can configure the device as either N-field-effect transistors (FET) or P-FET with a high current on/off ratio of over 105 by adjusting the three voltages (gate, source, and drain). Furthermore, we utilize these devices to demonstrate multifunctional wave modulator, low-static-power logic inverter (<5 pW), and combinational logic computing in the form of a compact complementary circuit. Our work would explore an efficient approach for implementing complementary circuits using 2D materials.

Nonvolatile reconfigurable polarization rotator at datacom wavelengths based on a Sb2Se3/Si waveguide

Silicon photonics has become a key platform for photonic integrated circuits (PICs) due to its high refractive index and compatibility with complementary metal-oxide-semiconductor manufacturing. However, the inherent birefringence in silicon waveguides requires efficient polarization management. Here, we report a reconfigurable polarization rotator (PR) using a Sb2Se3/Si waveguide operating at datacom wavelengths (1310 nm), providing nonvolatile switching with zero static power consumption. The polarization conversion relies on the interference of hybrid electric-magnetic (EH) modes, which can be reconfigured by changing the Sb2Se3 state between amorphous and crystalline. Our experimental device exhibits a polarization conversion efficiency (PCE) and a polarization extinction ratio (PER) as high as -0.08 dB and 17.65 dB, respectively, in a compact footprint of just 21 µm length. Therefore, the proposed reconfigurable PR offers a compact and energy-efficient solution for polarization management in silicon photonics, with potential applications in data communication networks and emerging applications benefiting from polarization information encodings, such as optical neural networks and quantum computing.

Dielectric Modulated Nanotube Tunnel Field-Effect Transistor with Core-Shell Cavity as a Label-Free Biosensor: Proposal and Analysis.

Dielectric Modulated Field-Effect Transistors (DMFETs) have emerged as promising candidates for label-free bioanalyte detection. However, the inherent short-channel effects in conventional DMFETs increase their static power dissipation significantly and limit their scalability and sensitivity. Therefore, FETs based on alternate conduction mechanism such as tunneling (TFETs), which are immune to the short-channel effects, appear to be a lucrative alternative to the MOSFETs for biosensing application. In this work, we propose a novel Dual Cavity Dielectric Modulated Nanotube Tunnel FET (DCDM NTTFET)-based label-free biosensor consisting of a Ge source and nanocavities within the core as well as a shell gate stack, which not only outperforms the conventional MOSFET and advanced nanowire (NW) TFET-based biosensors in terms of energy-efficiency and scalability but also exhibits a significantly high drain current sensitivity (SION = 2.9 × 108) and a threshold voltage sensitivity (SVth = 0.85), and a considerably high selectivity of more than 6 orders of magnitude. We also perform a comprehensive design space exploration for the proposed DCDM NTTFET and provide necessary design guidelines to further improve its performance considering the practical artifacts such as steric hindrance.

Analysis of etched drain based Cylindrical agate‐all‐around tunnel field effect transistor based static random access memory cell design

AbstractThis paper aims to propose a novel method for designing an static random access memory (SRAM) cell using an etched drain based Cyl GAA TFET with a hetero‐substrate material and an elevated density strip. The aim is to reduce power dissipation and improve stability, as demonstrated through analysis utilizing static noise margin (SNM) as well as N‐curve methods. With respect to the 16 nm MOSFET based SRAM cell, the proposed device‐based SRAM cell shows significant improvements with a 68.305% reduction in leakage power, a 15.58% increase in static voltage noise margin (SVNM), an 8.623% increase in static current noise margin (SINM), an 8.152% increase in write trip voltage (WTV), a 12.86% increase in write trip current (WTI), a 27.62% increase in static power noise margin (SPNM), and a 19.95% increase in write trip power (WTP). The design is implemented and analyzed using Cadence Virtuoso software, and a novel approach of look up tables and Verilog A is utilized for the device to circuit application. These results indicate promising advancements in the design of SRAM cells, which could have significant implications for the development of advanced computer systems.

Stochastic‐gradient‐based control algorithms for power quality enhancement in solar photovoltaic interfaced three‐phase distribution system

AbstractHere, stochastic‐gradient‐based adaptive control algorithms have been discussed and employed for power quality enhancement in a Photovoltaics (PV) integrated distribution system. Least mean square (LMS), least mean fourth (LMF), sign‐error LMS, and ‐normalised LMS (‐NLMS) have been implemented as control algorithms for the estimation of fundamental load current. The performances of these adaptive algorithms are compared under steady‐state and dynamic conditions under the non‐linear load conditions in a closed‐loop three‐phase system. The main aim of implementing these algorithms is reactive power compensation, power quality enhancement, and load balancing in a single‐stage three‐phase grid‐tied PV system. The hysteresis current control (HCC) technique is used to generate switching pulses for the three‐phase Distribution Static Power Compensator (DSTATCOM). An MPPT is also employed to ensure maximum power delivery from the solar PV array. PV integrated three‐phase single‐stage distribution system with adaptive control algorithms is implemented in MATLAB/Simulink environment as well as in experimental environment to achieve the goals per standard IEEE‐519.

Static Power Equipment for the Active Elimination of Harmonics from the National Energy Grid

Taking into account the long-term (2020-2050) Energy Strategy of Romania, and the Integrated National Plan in the Energy and Climate Changing 2021-2030, Dunărea de Jos University of Galati, utilizing the industrial partners, will conduct the applied industrial research to provide in the National Grid a clean energy, by harmonics mitigation. This paper deals with the Shunt Active Power solution to efficiently mitigate the current harmonics within the national power grid. Both numerical and experimental results are presented in this paper. The results of this paper are obtained by the beneficiary and the industrial partner of the „Knowledge transfer regarding the increase of energy efficiency and intelligent power systems” project, acronym CRESC-INTEL, within the POC Competitiveness Operational Program. The obtained results of this project will conduct one innovation-based ecosystem in the European Union research and technological development field. Innovative static power types of equipment ensure an increased energy efficiency of the power system with a high power factor. Based on the obtained prototype, a mass production of the innovative static power equipment will be delivered to the specific market, by complying with the available power quality standards. In this way, based on the static power equipment series production, by considering alternative power ranges, harmonic cleaning of the national grid is obtained.

Self-assembled monolayer gate doping and their detail deep cryogenic characterization of GaN/Si HEMTs

Wide bandgap GaN/AlGaN/GaN/SOI high-electron-mobility transistors (GaN/Si HEMTs) have recently grabbed interest in the semiconductor field as outstanding contenders for microwave and radio-frequency (RF) power amplification systems with their powerful capacities. Though the negative threshold voltage (Vth) property of GaN limits the practical application as an electronic system for static power consumption consideration, the current study demonstrates a novel method that can adjust Vth higher and without damaging the crystal lattice of the GaN channel materials by self-assembly monolayer doping. Also, the fabricated GaN/AlGaN/GaN/SOI HEMT devices exhibit excellent efficiency with enhancement of mobility and subthreshold slope in cryogenic temperatures using Fluorine-contained monolayer doping. This could unlock additional process options for the development of next-generation GaN/AlGaN/GaN/SOI HEMT with high mobility, catering to the advancements in 6G communication and circuits for low-orbit satellites.

Scalable on-chip multiplexing of silicon single and double quantum dots

Owing to the maturity of complementary metal oxide semiconductor (CMOS) microelectronics, qubits realized with spins in silicon quantum dots (QDs) are considered among the most promising technologies for building scalable quantum computers. For this goal, ultra-low-power on-chip cryogenic CMOS (cryo-CMOS) electronics for control, read-out, and interfacing of the qubits is an important milestone. We report on-chip interfacing of tunable electron and hole QDs by a 64-channel cryo-CMOS multiplexer with less-than-detectable static power dissipation. We analyze charge noise and measure state-of-the-art addition energies and gate lever arm parameters in the QDs. We correlate low noise in QDs and sharp turn-on characteristics in cryogenic transistors, both fabricated with the same gate stack. Finally, we demonstrate that our hybrid quantum-CMOS technology provides a route to scalable interfacing of a large number of QD devices, enabling, for example, variability analysis and QD qubit geometry optimization, which are prerequisites for building large-scale silicon-based quantum computers.

Development of Intelligent Testing and Evaluation System for Fracturing Pump

Abstract Fracturing truck is the key technical equipment for oil and gas production stimulation. Fracturing pump of fracturing truck is subjected to high pressure load for a long time during use. Due to the influence of many factors such as transportation and equipment aging, the performance of fracturing pump in field use is reduced and the output power is insufficient. In order to realize the on-site inspection of fracturing pump, a set of intelligent inspection and evaluation system of fracturing pump is developed. Through the establishment of the hardware test platform and the development of the software system, the intelligent inspection and evaluation system of fracturing pump with the features of one-click automatic detection, automatic analysis of performance indicators, intelligent prediction and maintenance of health status is realized. The system can support the static pressure test, water power test and overpressure protection test of 140MPa ultra-high pressure fracturing pump. Experimental tests show that the test accuracy of the equipment can effectively meet the detection and evaluation needs of the field fracturing truck, ensure the normal function through static pressure and water power detection, and determine the safety of the equipment through overpressure protection detection, which greatly improves the effect and efficiency of fracturing operations.

Photonic crystal topological interface state modulation for nonvolatile optical switching

Phase change materials (PCMs), characterized by high optical contrast (Δn>1), nonvolatility (zero static power consumption), and quick phase change speed (∼ns), provide new opportunities for building low-power and highly integrated photonic tunable devices. Optical integrated devices based on PCMs, such as optical switches and optical routers, have demonstrated significant advantages in terms of modulation energy consumption and integration. In this paper, we theoretically verify the solution for a highly integrated nonvolatile optical switch based on the modulation of the topological interface state (TIS) in the quasi-one-dimensional photonic crystal (quasi-1D PC). The TIS exciting wavelength changes with the crystalline level of the PCM. The extinction ratio (ER) of the topological optical switch is over 18 dB with a modulation length of 9 μm. Meanwhile, the insertion loss (IL) can be controlled within 2 dB. Furthermore, we have analyzed the impact of fabrication errors on the device’s performance. The obtained results show that, the topological optical switch, which changes its “on/off” state by modulating TIS, exhibits enhanced robustness to the fabrication process. We provide an interesting and highly integrated scheme for designing the on-chip nonvolatile optical switch. It offers great potential for designing highly integrated on-chip optical switch arrays and nonvolatile optical neural networks.

F-Bypass: a low-power network-on-chip design utilizing bypass to improve network connectivity

With the development of transistor feature size to nanometer level, static power consumption has gradually become the main factor affecting the overall power consumption of network on chip (NoC). Power gating is an effective technology to reduce static power consumption, but it also brings new challenges, such as BET violation, wake-up latency and network connectivity. Therefore, a power gating method is needed to improve NoC performance and reduce static power consumption. This paper proposes a low-power bypass method, namely Forwarding bypass (F-Bypass). First, F-Bypass adds bypass paths between all input and output ports and the network interface (NI), and connects the pop-up port and injection port in NI through the bypass path. When the router is powered off, F-Bypass performs wake-up-free packet transmission, which reduces the break-even time (BET) violation and cumulative wake-up latency while ensuring network connectivity. Secondly, This paper add the modified VC state table to NI, so that the power-off router can perform normal traffic control. Finally, a new wake-up criterion is proposed, which can effectively avoid the frequent wake-up of power-off routers, and the detailed hardware implementation of F-Bypass is provided.The simulation results under integrated traffic load show that compared with the traditional scheme, the delay of F-Bypass is reduced by 2.2%, the throughput is increased by 13.1%, and the total static power consumption is reduced by 75.2%. Key performance indicators are superior to other solutions, and the increased area cost is moderate.

A Universal Biocompatible and Multifunctional Solid Electrolyte in p-Type and n-Type Organic Electrochemical Transistors for Complementary Circuits and Bioelectronic Interfaces.

The development of soft and flexible devices for collection of bioelectrical signals is gaining momentum for wearable and implantable applications. Among these devices, organic electrochemical transistors (OECTs) stand out due to their low operating voltage and large signal amplification capable of transducing weak biological signals. While liquid electrolytes have demonstrated efficacy in OECTs, they limit its operating temperature and pose challenges for electronic packaging due to potential leakage. Conversely, solid electrolytes offer advantages such as mechanical flexibility, robustness against environmental factors, and ability to bridge the interface between rigid dry electronics systems and soft wet biological tissues. However, few systems have demonstrated generality and compatibility with a wide range of state-of-the-art organic mixed ionic-electronic conductors (OMIECs). This paper introduces a highly stretchable, flexible, biocompatible, self-healable gelatin-based solid-state electrolyte, compatible with both p- and n-type OMIEC channels while maintaining high performance and excellent stability. Furthermore, this nonvolatile electrolyte is stable up to 120°C and exhibits high ionic conductivity even in dry environment. Additionally, an OECT-based complementary inverter with a record-high normalized-gain of 228 V-1 and a corresponding ultralow static power consumption of 1 nW is demonstrated. These advancements pave the way for versatile applications ranging from bioelectronics to power-efficient implants.

Overload suppression technology for traction transformers based on railway static power conditioner

Overload suppression technology for traction transformers based on railway static power conditioner

Fully tunable Fabry-Pérot cavity based on MEMS Sagnac loop reflector with ultra-low static power consumption

The Fabry-Pérot interferometer, a fundamental component in optoelectronic systems, offers interesting applications such as sensors, lasers, and filters. In this work, we show a tunable Fabry-Pérot cavity consisting of tunable Sagnac loop reflectors (SLRs) and phase shifters based on electrostatic microelectromechanical (MEMS) actuator. The fabrication process of the device is compatible with the standard wafer-level silicon photonics fabrication processes. This electrostatic actuation mechanism provides well-balanced, scalable pathways for efficient tuning methodologies. The extinction ratio of the continuously tunable SLRs’ reflectivity is larger than 20 dB. Full 2π phase shifting is achieved, and response times of all the components are less than 25 μs. Both actuators have extremely low static power, measuring under 20 fW and the energy needed for tuning is both below 20 pJ.

Energy-Efficient Reservoir Computing Based on Solution-Processed Electrolyte/Ferroelectric Memcapacitive Synapses for Biosignal Classification.

The classification of critical physiological signals using neuromorphic devices is essential for early disease detection. Physical reservoir computing (RC), a lightweight temporal processing neural network, offers a promising solution for low-power, resource-constrained hardware. Although solution-processed memcapacitive reservoirs have the potential to improve power efficiency as a result of their ultralow static power consumption, further advancements in synaptic tunability and reservoir states are imperative to enhance the capabilities of RC systems. This work presents solution-processed electrolyte/ferroelectric memcapacitive synapses. Leveraging the synergistic coupling of electrical double-layer (EDL) effects and ferroelectric polarization, these synapses exhibit tunable long- and short-term plasticity, ultralow power consumption (∼27 fJ per spike), and rich reservoir state dynamics, making them well-suited for energy-efficient RC systems. The classifications of critical electrocardiogram (ECG) signals, including arrhythmia and obstructive sleep apnea (OSA), are performed using the synapse-based RC system, demonstrating excellent accuracies of 97.8 and 80.0% for arrhythmia and OSA classifications, respectively. These findings pave the way for developing lightweight, energy-efficient machine-learning platforms for biosignal classification in wearable devices.

(Invited) Ferroelectric Nonvolatile Capacitive Synapse for Charge Domain Compute-in-Memory

The rise of Artificial Intelligence has led to an increased demand for computing hardware which can handle data intensive tasks in an energy efficient manner. Compute-in-memory architecture which combines information processing and data storage at the same location and specializes in Multiply-and-Accumulate (MAC) operation has emerged as an attractive candidate to meet this demand. Non-volatile capacitive (nvCAP) devices are investigated to realize the synaptic devices to enable CIM in charge-domain-computing. Charge-domain-CIM works as follows: The synaptic weights of a neural network are stored as the capacitance state of the nvCAP device in a crossbar array. The input of the neural network is applied as voltages to the crossbar array, and the resulting charges are summed up as the MAC operation. The nvCAP synaptic devices also provides benefits over traditional resistive synapses such as: only static power consumption, negligible sneaky current, suppressed read-disturb due to small-signal-read out. Recently, the Ferroelectric Field Effect Transistor (FeFET) has been demonstrated to operate in nvCAP mode, with S-D terminal of the FET shorted and Body-Floating. Here, the Field Effect Transistor part exhibits a gate voltage-dependent capacitance behavior, where the high capacitance originates from the transistor gate area, while the low capacitance originates from the overlap region between the gate oxide and source-drain region of FET. The ferroelectric layer part introduces a lateral shift in the C-V curve of FET, leading to either a high (CON) or low capacitance (COFF) state at 0V that can be tuned by an applied electric field. The CON/COFF ratio of the device can be designed as-per the application by increasing the channel area and reducing the overlap length. For a robust and consistent performance in CIM, reliability aspects of ferroelectric nvCAP are investigated. The FeFET in nvCAP mode demonstrates an initial endurance of 106 Program-Erase cycles while maintaining the ON/OFF >5. It is found that a CV sweep performed on the device help recover the performance. By performing repeated endurance-recovery operation, a recovered endurance of 108 cycles is achieved. The nvCAP device demonstrates memory retention of at least 1 day @85C for all fresh, fatigued and recovered states of the device. The nvCAP device also shows multi-level-cell capabilities for atleast 4 levels by changing the Program voltages. Figure 1

Regional analysis and optimization control of static power stable operation of grid-connected converter under weak grid

Regional analysis and optimization control of static power stable operation of grid-connected converter under weak grid

Solution to SRAM static power consumption with MTCMOS

The rapid growth of mobile devices has led to an increasing demand for battery life and energy efficiency in recent years, the reduction of circuit power consumption has become extremely crucial. SRAM has become an indispensable component of modern System-on-Chip (SoC) designs, and reducing its power consumption holds significant importance in minimizing overall chip power consumption. On the other hand, as manufacturing processes advance, static power consumption resulting from leakage currents has gradually emerged as a primary source of power consumption. This paper analyzes the power composition of SRAM, provides a detailed explanation of the principles and influencing factors of MTCMOS design technology, and conducts modeling analysis on 6T SRAM based on MTCMOS. In the modeling analysis, we compare the leakage current and static power reduction effects of 6T SRAM using four different process technologies: 28nm, 40nm, 65nm, and 90nm. From the data, it can be observed that MTCMOS has a notable effect in reducing leakage current for 6T SRAM across various process technologies. Comparing 6T SRAM of different process technologies, we can roughly see that the power reduction effect reaches a peak and gradually decreases. However, due to the lack of more advanced process libraries, we cannot further validate whether this inference is accurate.