Static Power Consumption Research Articles

3T-SAPON technique to reduce Power Consumption

Scaling down CMOS technology has rapidly improved cost, area effectiveness, switching speed of the circuits & high device reliability. However, scaling has an immense impact on static power consumption in VLSI circuits. For battery operating applications higher power dissipation is not desirable because it reduces the efficiency and cooling effects of the battery. Thus, designing a low-power consuming circuit has become the major criteria in circuit designs. A new circuit model called 3T-SAPON is designed to reduce static power consumption. 3T-SAPON technique power consumption has been reduced around 45%. Using this technique inverter, NAND are implemented and compared with some of the existing standard techniques like LCNT, LECTOR, ONOFIC and SAPON. All these circuits are simulated in Cadence 90nm technology.

Dense, 11 V-Tolerant, Balanced Stimulator IC with Digital Time-Domain Calibration for 100 nA Error.

This article presents a multichannel neurostimulator implementing a novel charge balancing technique to achieve maximal integration. Safe neurostimulation demands accurate charge balancing of the stimulation waveforms to prevent charge build-up on the electrode-tissue interface. We propose digital time-domain calibration (DTDC), which adjusts the second phase of the biphasic stimulation pulses digitally, based on a one-time characterization of all stimulator channels with an on-chip ADC. Accurate control of the stimulation current amplitude is loosened in exchange for time-domain corrections, relieving circuit matching constraints and consequentially saving channel area. A theoretical analysis of DTDC is presented, establishing expressions for the required time resolution and the new, relaxed circuit matching constraints. To validate the DTDC principle, a 16-channel stimulator was implemented in 65 nm CMOS, requiring only 0.0141 mm 2 area/channel. Despite being implemented in a standard CMOS technology, 10.4 V compliance is achieved for compatibility with high-impedance microelectrode arrays typical for high-resolution neural prostheses. To the authors' knowledge, this is the first stimulator in a 65 nm low-voltage process achieving over 10 V output swing. Measurements after calibration show the DC error is successfully reduced below 96 nA on all channels. Static power consumption is 20.3 µW/channel.

A Transient-Enhanced Autonomous Current Adaptation Buffer Amplifier

This paper proposes a transient enhanced autonomous current adaptation buffer amplifier (ACABA) that effectively resolves the slew rate degradation problem observed in the previous design. The proposed circuit enhances the transient responses, achieving faster step responses, superior linearity, and higher power efficiency. The cause of the degradation in the previous work has been elucidated, and a transient enhancement circuit is proposed to circumvent the slewing bottleneck. A prototype chip has been designed and fabricated in a 0.35μm CMOS process. From measurements, the proposed circuit improves settling time by 62.1%, enhances slew rate by 3.1 times, and reduces total harmonic distortion (THD) by 17 dB without extra static power consumption. With a 2.5V supply voltage, the proposed buffer amplifier allows a maximum input signal amplitude of 2.3 V with the THD below -60dB. Furthermore, the enhanced buffer amplifier exhibits the best power efficiency in both small-signal and large-signal performance compared to other state-of-the-art designs.

Applications of CMOS image sensors: Applications and innovations

As semiconductor production processes continue to advance, CMOS image sensors are becoming increasingly popular and are gradually replacing traditional CCD sensors as the mainstream option in the market. Because CMOS image sensors adopt the standard CMOS semiconductor production process, which provides advantages such as low static power consumption, large noise tolerance, strong anti-interference ability, and fast working speed. This article is going to provide an overview of CMOS image sensors and examine their various applications. To achieve this, this article will provide some background information on CMOS image sensors, including a discussion of their structure, components, and working principles. A comprehensive literature review was conducted to explore the characteristics and benefits of CMOS image sensors in applications such as intelligent surveillance systems (ISS), space, and medical. This paper also discusses recent advances in CMOS image sensor technology, namely backside illumination, global shutter, and 3D imaging, and their impact on various industries. Despite the advantages of CMOS image sensors, they still have some limitations and shortcomings. Therefore, further progress in industrial development is necessary to improve the quality of these products.

Power-Efficient Multisensory Reservoir Computing Based on Zr-Doped HfO2 Memcapacitive Synapse Arrays.

Hardware implementation tailored to requirements in reservoir computing would facilitate lightweight and powerful temporal processing. Capacitive reservoirs would boost power efficiency due to their ultralow static power consumption but have not been experimentally exploited yet. Here, this workreports an oxide-based memcapacitive synapse (OMC) based on Zr-doped HfO2 (HZO) for a power-efficient and multisensory processing reservoir computing system. The nonlinearity and state richness required for reservoir computing could originate from the capacitively coupled polarization switching and charge trapping of hafnium-oxide-based devices. The power consumption (≈113.4 fJ per spike) and temporal processing versatility outperform most resistive reservoirs. Thissystem is verified by common benchmark tasks, and it exhibits high accuracy (>94%) in recognizing multisensory information, including acoustic, electrophysiological, and mechanic modalities. As a proof-of-concept, a touchless user interface for virtual shopping based on theOMC-based reservoir computing system is demonstrated, benefiting from its interference-robust acoustic and electrophysiological perception. Theseresults shed light on the development of highly power-efficient human-machine interfaces and machine-learning platforms.

Integrated Bragg grating filters based on silicon-Sb2Se3 with non-volatile bandgap engineering capability.

Integrated optical filters show outstanding capability in integrated reconfigurable photonic applications, including wavelength division multiplexing (WDM), programmable photonic processors, and on-chip quantum photonic networks. Present schemes for reconfigurable filters either have a large footprint or suffer from high static power consumption, hindering the development of reconfigurable photonic integrated systems. Here, a reconfigurable hybrid Bragg grating filter is elaborately designed through a precise, modified coupling mode theory. It is also experimentally presented by integrating non-volatile phase change material (PCM) Sb2Se3 on silicon to realize compact, low-loss, and broadband engineering operations. The fabricated filter holds a compact footprint of 0.5 µm × 43.5 µm and maintains a low insertion loss of < 0.5 dB after multiple levels of engineering to achieve crystallization. The filter is able to switch from a low-loss transmission state to the Bragg reflection state, making it a favorable solution for large-scale reconfigurable photonic circuits. With a switching extinction ratio over 30 dB at 1504.85 nm, this hybrid filter breaks the tradeoff between insertion loss and tuning range. These results reveal its potential as a new candidate for a basic element in large-scale non-volatile reconfigurable systems.

Design and Analysis of Static Random-Access Memory FinFET Circuit Using Self Controlled Voltage Level Controller

Researchers in the field of device research are always searching for a device that meets certain criteria, such as having low leakage and a low threshold voltage, without sacrificing performance. This pursuit has led to the development of numerous gate architectures. As a result of the enormous size of the static random-access memory (SRAM), its yield and leakage power consumption account for the majority of the chip’s total yield and leakage power consumption respectively. However, as CMOS technology continues to grow in the sub-65 nanometer domain to lower the cost of transistors and the dynamic power, it presents a number of issues on the design of SRAM. In this paper, a 6T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed. The structure is based on modifying a recently proposed 6T cell which uses high and low VTH transistors to improve the read and write stability. Also, the changes of cell parameters when the temperature rises from 40 °C to 100 °C are investigated. Finally, the write margin as well as the read and hold SNMs of the cell are studied at two supply voltages of 400 mV and 500 mV.

Optimization of Half-Flux-Quantum Circuits Composed of π-Shift and Conventional Josephson Junctions

We report optimization of half-flux-quantum (HFQ) circuits composed of SQUIDs containing conventional Josephson junctions and π-shift magnetic Josephson junctions. The SQUID can act as a Josephson junction with an extremely small critical current and be easily switched by a weak driving force with the assistance of the circulating current that is induced due to the π-shift and quantization conditions. It leads to a drastic reduction of both static and dynamic power consumption. However, the parameter margins of the HFQ circuits obtained so far is narrow compared with conventional single-flux-quantum circuits. Since HFQ circuits use many circuit elements and require the two junctions in the SQUID to switch alternately and symmetrically, circuit parameter optimization is much more difficult. In this study, we developed an optimization tool for HFQ circuits, including operation judgment and margin calculation. We improved the critical margin of the HFQ Josephson transmission line to 39%. We also optimized the HFQ splitter, confluence buffer, and D flip-flop. We discuss design guidelines for HFQ circuits based on our systematic exploration of the optimized circuit parameter sets. We suggest that the optimized loop inductances are around 0.5 and 1.5 of Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> /2 for data transmission and storage, respectively.

Contact-engineered reconfigurable two-dimensional Schottky junction field-effect transistor with low leakage currents

Two-dimensional (2D) materials have been considered promising candidates for future low power-dissipation and reconfigurable integrated circuit applications. However, 2D transistors with intrinsic ambipolar transport polarity are usually affected by large off-state leakage currents and small on/off ratios. Here, we report the realization of a reconfigurable Schottky junction field-effect transistor (SJFET) in an asymmetric van der Waals contact geometry, showing a balanced and switchable n- and p-unipolarity with the Ids on/off ratio kept >106. Meanwhile, the static leakage power consumption was suppressed to 10−5 nW. The SJFET worked as a reversible Schottky rectifier with an ideality factor of ~1.0 and a tuned rectifying ratio from 3 × 106 to 2.5 × 10−6. This empowered the SJFET with a reconfigurable photovoltaic performance in which the sign of the open-circuit voltage and photo-responsivity were substantially switched. This polarity-reversible SJFET paves an alternative way to develop reconfigurable 2D devices for low-power-consumption photovoltaic logic circuits.

Cascaded Logic Gates Based on High-Performance Ambipolar Dual-Gate WSe2 Thin Film Transistors.

Ambipolar dual-gate transistors based on low-dimensional materials, such as graphene, carbon nanotubes, black phosphorus, and certain transition metal dichalcogenides (TMDs), enable reconfigurable logic circuits with a suppressed off-state current. These circuits achieve the same logical output as complementary metal-oxide semiconductor (CMOS) with fewer transistors and offer greater flexibility in design. The primary challenge lies in the cascadability and power consumption of these logic gates with static CMOS-like connections. In this article, high-performance ambipolar dual-gate transistors based on tungsten diselenide (WSe2) are fabricated. A high on-off ratio of 108 and 106, a low off-state current of 100 to 300 fA, a negligible hysteresis, and an ideal subthreshold swing of 62 and 63 mV/dec are measured in the p- and n-type transport, respectively. We demonstrate cascadable and cascaded logic gates using ambipolar TMD transistors with minimal static power consumption, including inverters, XOR, NAND, NOR, and buffers made by cascaded inverters. A thorough study of both the control gate and the polarity gate behavior is conducted. The noise margin of the logic gates is measured and analyzed. The large noise margin enables the implementation of VT-drop circuits, a type of logic with reduced transistor number and simplified circuit design. Finally, the speed performance of the VT-drop and other circuits built by dual-gate devices is qualitatively analyzed. This work makes advancements in the field of ambipolar dual-gate TMD transistors, showing their potential for low-power, high-speed, and more flexible logic circuits.

Design of a high performance CNFET 10T SRAM cell at 5nm technology node

This article proposes a CNFET 10T SRAM cell based on Stanford Virtual Source model at 5nm technology node, through optimization design and simulation analysis to select optimum gate widths of transistors to ensure best performance in terms of stability, speed and power consumption. We compare the proposed 10T CNFET SRAM with the optimized 6T CNFET SRAM in [9]. It was found that the timing and power characteristics of the proposed 10T SRAM cell is better than that of the 6T structure, the static power consumption is greatly reduced while the RSNM is improved by 93.5%, read and write EDP are improved by 68.5% and 96%, respectively.

Non-volatile electrically programmable integrated photonics with a 5-bit operation

Scalable programmable photonic integrated circuits (PICs) can potentially transform the current state of classical and quantum optical information processing. However, traditional means of programming, including thermo-optic, free carrier dispersion, and Pockels effect result in either large device footprints or high static energy consumptions, significantly limiting their scalability. While chalcogenide-based non-volatile phase-change materials (PCMs) could mitigate these problems thanks to their strong index modulation and zero static power consumption, they often suffer from large absorptive loss, low cyclability, and lack of multilevel operation. Here, we report a wide-bandgap PCM antimony sulfide (Sb2S3)-clad silicon photonic platform simultaneously achieving low loss (<1.0 dB), high extinction ratio (>10 dB), high cyclability (>1600 switching events), and 5-bit operation. These Sb2S3-based devices are programmed via on-chip silicon PIN diode heaters within sub-ms timescale, with a programming energy density of sim 10,{fJ}/n{m}^{3}. Remarkably, Sb2S3 is programmed into fine intermediate states by applying multiple identical pulses, providing controllable multilevel operations. Through dynamic pulse control, we achieve 5-bit (32 levels) operations, rendering 0.50 ± 0.16 dB per step. Using this multilevel behavior, we further trim random phase error in a balanced Mach-Zehnder interferometer.

Redox‐Mediated Single‐Molecule Transistor with A Subthreshold Swing Down To 120 mV Decade−1

AbstractThe single‐molecule electronic devices offer the ultimate solution to miniaturize integrated circuits, and subthreshold swing (SS) is the key indicator of the power consumption for single‐molecule transistors but is still quite restricted. In this study, the redox‐mediated single‐molecule transistor with a SS down to 120 mV decade−1 in the faradaic potential region via the electrochemical‐STM break junction (EC‐STM‐BJ) technique is fabricated. With an off‐state leakage current of less than 10 pA and an on/off ratio of 100, the balance between low static power consumption and a high switching ratio is achieved. The theoretical investigations reveal that the conductance tuning is from the difference of transmission in the redox process. The study provides a new strategy for the design of single‐molecule transistors with promising SS, which is essential for the potential application of single‐molecule devices.

MRAM-Based Cache System Design and Policy Optimization for RISC-V Multi-Core CPUs

On-chip cache, being the crucial constituent of central processing unit (CPU), accounts for a pivotal portion of the system’s overall power consumption. The typical SRAM-based cache is vulnerable to high static leakage power consumption, while multiple challenges encountered in scaling up its capacity. In the paper, magnetic random-access-memory (MRAM) cache is considered as a promising candidate in RISC-V CPU systems. After analyzing the performances of single-core, dual-core, quad-core, and octa-core systems, a quad-core RISC-V based CPU system with a two- level hierarchical cache structure is designed, in which Spin-Orbit Transfer (SOT)-MRAM is adopted as the L1 private cache and Spin-Transfer Torque (STT)-MRAM as the L2 shared cache. Details on the microarchitecture of the multi-core CPU design are provided. Energy evaluation shows that this quad-core cache system can achieve 66.4% leakage power saving and 34.5% total power saving compared to SRAM. For high efficiency of data-exchange in the novel MRAM CPU systems, three types of characteristics optimizing methods are proposed. An optimized cache-coherency protocol incorporating non-inclusive policy is proposed. The quad-core system is updated by adding the coherence control module and a directory in the design scheme. The simulation results on multiple dimensions show that the policy of the hybrid MRAM memory is a promising candidate for multi-core RISC-V system, with the benefits of low-power consumption and high hit rate. Finally, the peripheral circuitry and manufacturing cost for the implementation of the MRAM cache is discussed in the paper.

MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM

Conventional computing architectures based on the von Neumann structure are suffering from the severe ‘memory wall’ issue due to the isolation and speed mismatch between memory and processor. As a promising solution, the concept of logic in-memory (LiM) has been proposed to effectively reduce the overhead of data migration and has been extensively studied in various memory technologies such as SRAM, DRAM, MRAM, ReRAM, etc. Among them, SOT-MRAM combines the advantages of non-volatility, low static power consumption, ultra-fast read/write speed, and high density, has emerged as one of the most promising candidates for low-power LiM implementations. In this paper, four in-memory logic operations, AND, OR, MAJ and full-addition (FA), are proposed based on the Unipolar Switching (US) SOT-MRAM devices. Incorporating the emerging switching behavior of SOT-MRAM, these operations can be performed with the basic memory access operations (read/write) with negligible modifying peripheral circuits. Meanwhile, by optimizing the operation steps, the performance degradation caused by the instability of SOT-MRAM device can be minimized in the proposed LiM architecture. Detailed simulation results show that the proposed design can reduce the latency (energy) of AND, OR operations at least by 71.2%, 74.4% (30.0%, 35.4%) compared with the existing SRAM and STT-MRAM designs. For MAJ and FA operations, the performance is improved by at least 34.7% and 44.8% compared to the existing design. The robustness of our design is demonstrated by the 100% pass of the 1000 samples Monte Carlo simulations for the sufficient switching current margin and the effectiveness of basic operations.

P‐19: A Design and application of MIP special driving system for low power Glass‐based products

In this paper, a design and application of low power handwritten tablet is proposed. Based on glass‐based MIP low power LCD technology for a 8‐inch product , the multi‐lane SPI series parallel decoding circuit is used to improve the decoding speed of image data transmission, At the same time, it can be refreshed in units of 1 line for partial refresh by means of address decoding. Because the communication and decoding interface of MIP LCD technology is a non‐general interface, an adaptive dedicated driving system is proposed simultaneously, including SOC, MCU, MIP LCD screen, stylus and touch sensor processing. In this driving system, SOC is transmitted to MCU through USB HS, and MCU drives MIP display by customized SPI interface. It can realize the global refresh, partial refresh and stylus touch through data processing which matching the unique data requirements of MIP and adopting multi‐buffer and thread separation. The low‐ power handwritten tablet solution proposed in this paper can significantly reduce power consumption with static power consumption of 25uW and full‐screen refresh rate reach 25Hz while partial refresh rate (100 lines) can be up to 300Hz. Combined with 8color display and stylus partial refresh application, the display content is richer and the response speed is increased by 42.8%, user experience is greatly improved.

A highly sensitive vertical plug-in source drain high Schottky barrier bilateral gate controlled bidirectional tunnel field effect transistor.

In this article, we propose a highly sensitive vertically plug-in source drain contacts high Schottky barrier based bilateral gate and assistant gate controlled bidirectional tunnel field Effect transistor (VPISDC-HSB-BTFET). It can achieve much more sensitive forward current driving ability than the previously proposed High Schottky barrier source/drain contacts based bilateral gate and assistant Gate controlled bidirectional tunnel field Effect transistor (HSB-BTFET). Silicon body of the proposed VPISDC-HSB-BTFET is etched into a U-shaped structure. By etching both sides of the silicon body to form vertically plug-in source drain contacts, the source and drain electrodes are plugged into a certain height of the vertical parts of both sides of the U-shaped silicon body. Thereafter, the efficient area of the band-to-band tunneling generation region near the source drain contacts is significantly increased, so as to achieve sensitive ON-state current driving ability. Comparing to the mainstream FinFET technology, lower subthreshold swing, lower static power consumption and Higher Ion-Ioff ratio can be achieved.

Energy efficient IPC based dual compression for endurance enhancement of NVRAM as main memory in embedded devices

AbstractThe Non‐Volatile Random Access Memory (NVRAM) is recently identified as the most upcoming main memory technology in Embedded and Internet of Things (IoT) systems due to its appealing qualities like zero static power consumption and great memory cell density. On the other hand, most NVRAMs have low write endurance due to workload‐induced write variance, leading to more write activity at a few blocks of memory than the other blocks. Improving the endurance of NVRAM on embedded architectures is very critical due to the limited constraints of Embedded architectures. The main goal of this paper is to address the complexity of NVRAM designs, with a focus on embedded boards, and to create a prototype that enhances NVRAM endurance using a compression technique. Furthermore, this framework is not particular to a single NVRAM device. An Instruction Per Cycle based Dynamic Pattern Compression (IPC_DPC) model is developed to address NVRAM's high write latency and low endurance. The primary goal of the proposed IPC_DPC model is to minimize the energy utilization and latency of heavy workloads during the execution by pre‐determining the workload's instruction cycles. The IPC_DPC model initially divides the Low IPC and High IPC workloads and then compresses the workloads dynamically based on their IPC values compared to the threshold factor. As a result, IPC_DPC improves the compression ratio and reduces the write latencies associated with traditional compressors, significantly reducing the write activity and improving the lifetime of NVRAM. We implemented the proposed IPC_DPC model using GEM5 with a Raspberry Pi board and took IoMT, MiBench, and EEMBC benchmarks for evaluation. Compared to FPC, BDI, FNW, and DFPC models, the proposed IPC_DPC model is shown to be more efficient in terms of compression ratio (56.05%) and energy reduction (17%).

A 0.15-to-0.5 V Body-Driven Dynamic Comparator with Rail-to-Rail ICMR

In this paper, a novel dynamic body-driven ultra-low voltage (ULV) comparator is presented. The proposed topology takes advantage of the back-gate configuration by driving the input transistors’ gates with a clocked positive feedback loop made of two AND gates. This allows for the removal of the clocked tail generator, which decreases the number of stacked transistors and improves performance at low VDD. Furthermore, the clocked feedback loop causes the comparator to behave as a full CMOS latch during the regeneration phase, which means no static power consumption occurs after the outputs have settled. Thanks to body driving, the proposed comparator also achieves rail-to-rail input common mode range (ICMR), which is a critical feature for circuits that operate at low and ultra-low voltage headrooms. The comparator was designed and optimized in a 130-nm technology from STMicroelectronics at VDD=0.3 V and is able to operate at up to 2 MHz with an input differential voltage of 1 mV. The simulations show that the comparator remains fully operational even when the supply voltage is scaled down to 0.15 V, in which case the circuit exhibits a maximum operating frequency of 80 kHz at Vid=1 mV.

A 17.6-Bit 800-SPS Energy-Efficient Read-Out IC With Input Impedance Boosting

A 17.6-bit, 800-sample-per-second (SPS) read-out integrated circuit has been implemented for a bridge sensor. The read-out integrated circuit has a capacitively-coupled instrumentation amplifier (CCIA) with a sensor offset voltage compensation circuit, an amplifier offset voltage compensation circuit, and an input impedance boosting loop (IBL). Followed by the CCIA, a programmable-gain third-order discrete-time incremental delta-sigma (ΔΣ) analog-to-digital converter (ADC) with an output data-rate of 12.8 kHz shortens the sensing time to reduce the static power consumption of the resistive bridge sensor and the read-out IC. To boost the input impedance of the CCIA, the system-level input and output choppers operate at a frequency of 12.8 kHz. The ΔΣ modulator converts the modulated signal to digital with a sampling clock of 4 MHz. The system-level chopping reduces the residual offset and the low-frequency noise with an on-chip cascade of integrators (CoI) filter. Implemented in a 0.13 μm CMOS process, the read-out circuit achieves an input impedance of 22 MΩ at a data-rate of 800 SPS, a sensor offset compensation range of ± 350 mV, a maximum effective resolution of 17.6 bits, and an input-referred noise of 1.72 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</sub> at a gain of 128. It draws an average current of 106.3 μA from a 3 V supply and 1.3 μA from a 1.5 V supply.