Standard Complementary Metal Oxide Semiconductor Research Articles

Sub‐mW cognitive CMOS frequency down‐converter for internet of things

In this study, a suitable sub-mW frequency down converter for internet of things is presented. It is based on a single balanced switched transconductance mixer driven by a current-reuse LC voltage controlled oscillator (LC-VCO). For cognitive radio demonstration, the frequency converter is implemented with a tunable low-noise amplifier (LNA) in 0.13 µm standard complementary metal oxide semiconductor (CMOS) technology. Post-layout simulations return a gain conversion of 27 dB with a single-sideband noise figure of 8 dB (LNA included) for a consumption of 0.97 mW under a voltage supply of 1.2 V and an active area of 0.4 mm2. The stand-alone LC-VCO prototype exhibits a measured phase noise of −102 dBc/Hz at 1 MHz offset while showing −114 dBc/Hz in the post-layout simulation. The LC-VCO measured power consumption is only 260 µW from 1 V voltage supply with an active area of 0.173 mm2.

Design of Common-gate with Common-source Active Balun for WiMAX Receiver Front-end

This paper presents a design and simulation study of a common-gate with common-source active balun circuit implemented in a standard 90-nm complementary metal-oxide semiconductor (CMOS) process. The active balun design is intended for worldwide interoperability for microwave access (WiMAX) application, with operating frequency of 5.8 GHz and supply voltage of 1 V. Measurements are taken for parameters namely gain difference, phase difference, and noise figure. The common-source active balun design achieved a minimal gain difference of 0.04 dB, phase difference of 180 ± 1.5 degrees, and noise figure of 8.76 dB, which are comparable to past active balun designs and researches. The design eventually achieved a low power consumption of 4.45 mW.

Photoelectric Dual Control Negative Differential Resistance Device Fabricated by Standard CMOS Process

To prepare a desired negative differential resistance (NDR) device by standard complementary-metal–oxide–semiconductor (CMOS) process, a photoelectric dual control NDR device with a PNP bipolar-junction-transistor (BJT) and an NPN BJT was designed and fabricated by using the Si-base standard 0.18 μ m CMOS process without any process modification and a special substrate. In order to reduce the valley current under optical control, a metal mask was added to the NDR device. The results show that the device exhibits good NDR characteristics under either voltage-control or photo-control. Under voltage-control, a low volley current (0.23 pA) and a high peak-to-valley current ratio (1.4 × 1010) are obtained at less than 1 V. Under photo-control, the two parameters obtained at less than 0.5 V, are 37 nA and 4827, respectively. Also, the device displays fine S -type NDR characteristics and nice maintaining response function under photo-control. These superior photoelectric NDR characteristics endow the device with greatly potential application in the photoelectric logic circuits.

Direct integration of piezoactuator array with active-matrix oxide thin-film transistors using a low-temperature solution process

The integration of a thin-film piezoelectric actuator with standard CMOS (Complementary Metal-Oxide-Semiconductor) technology has attracted many practical interests for totally integrated smart devices such as electronics, microfluidics, sensors and actuators. However, the major obstacle of the integration lies in high annealing temperature required for crystallization of piezoelectric thin-films (600–750 °C), which leads to degradation of back circuitry. This paper reports, for the first time, a successful direct integration of lead-zirconium-titanate (PZT) thin-film, the piezoelectric with the greatest commercial applicability, with an active-matrix oxide thin-film transistor (TFT) using a low-temperature (450 °C) solution-processable PZT thin-film. The actuation of the PZT actuator array, electrically driven by the active-matrix TFT, was confirmed. The proposed device can be used in various applications such as micropumps/valves, microfluidic control, energy harvesting, sensors and the like.

A fuzzy Anti-lock braking system (ABS) controller using CMOS circuits

In this paper, an Anti-lock braking system (ABS) is designed using a fuzzy logic controller (FLC). The FLC is designed in 0.35 μm standard CMOS process and this design of the circuit makes it having high speed and low power consumption. Also, all the controlling signals and input signals are in voltage form and there is no need for digital programming. Voltage mode design of the circuits leads to the convenient use of FLC with sensors. The objective function is designed to keep the wheel slip to a desired level so that maximum wheel tractive force and maximum vehicle deceleration are achieved. By training this function to the Adaptive Nero-Fuzzy Inference System (ANFIS) of MATLAB software the main parameters of fuzzy controller singletons and shape of Membership Function Generators (MFGs) are measured, then all the circuits of the proposed fuzzy logic controller is designed using Complementary Metal-Oxide-Semiconductor (CMOS) circuits, at the end simulation results of the fuzzy logic controller using Hspice simulator and BSIM3v3 (Berkeley Short-Channel Insulated gate field effect transistor Model) parameters verifies the performance and functionality of the design.

Optimization of a Piezoelectric Energy Harvester and Design of a Charge Pump Converter for CMOS-MEMS Monolithic Integration.

The increasing interest in the Internet of Things (IoT) has led to the rapid development of low-power sensors and wireless networks. However, there are still several barriers that make a global deployment of the IoT difficult. One of these issues is the energy dependence, normally limited by the capacitance of the batteries. A promising solution to provide energy autonomy to the IoT nodes is to harvest residual energy from ambient sources, such as motion, vibrations, light, or heat. Mechanical energy can be converted into electrical energy by using piezoelectric transducers. The piezoelectric generators provide an alternating electrical signal that must be rectified and, therefore, needs a power management circuit to adapt the output to the operating voltage of the IoT devices. The bonding and packaging of the different components constitute a large part of the cost of the manufacturing process of microelectromechanical systems (MEMS) and integrated circuits. This could be reduced by using a monolithic integration of the generator together with the circuitry in a single chip. In this work, we report the optimization, fabrication, and characterization of a vibration-driven piezoelectric MEMS energy harvester, and the design and simulation of a charge-pump converter based on a standard complementary metal–oxide–semiconductor (CMOS) technology. Finally, we propose combining MEMS and CMOS technologies to obtain a fully integrated system that includes the piezoelectric generator device and the charge-pump converter circuit without the need of external components. This solution opens new doors to the development of low-cost autonomous smart dust devices.

Design of Common-Source/Drain Active Balun Using 90nm CMOS Technology

This research paper presents a design and study of a common-source/drain active balun circuit implemented in a standard 90-nm complementary metal-oxide semiconductor (CMOS) technology. The active balun design is intended for worldwide interoperability for microwave access (WiMAX) application, with operating frequency of 5.8GHz and supply voltage of 1V. Measurements are taken for parameters namely gain difference, phase difference, and noise figure. The common-source active balun design achieved a minimal gain difference of 0.016dB, phase difference of 180° ± 7.1°, and noise figure of 7.42-9.85dB, which are comparable to past active balun designs and researches. The design eventually achieved a low power consumption of 2.56mW.

CMOS Light Field Image Sensor Building Block for Detection of Multicolor LED Blink Sequence From Heterogeneous Locations

A light field image sensor is fabricated on a standard complementary metal–oxide-semiconductor (CMOS) process. The sensor uses two grating layers of various layer-to-layer distances to take advantage of Talbot effect. The horizontal placement of the upper grating relative to the lower one has three types of configurations. By shifting the upper grating to the left or right or aligned position relative to the lower grating, light incident from left, right, and center can be differentiated. Furthermore, color selectivity is analyzed by varying grating slit spacing to favor a particular color’s wavelength to reach Talbot depth. We designed photodiodes each having area of $14\times15\,\,\mu {\mathrm{ m}}^{2}$ . We used a 180-nm five-metal CMOS process and achieved an angle differentiation accuracy error within 1.8° for the direct incidence on aligned configuration and within 3.6° of the expected angle for the left- and right-shifted configurations. In addition, we experimented with applying various wavelengths of light even to sensor structures favoring other wavelengths to analyze their effects. Combining these sensor characteristics, we show that red, green, and blue lights, clustered together at three different locations, can be recognized by a set of light field sensors. The sensor set can differentiate 6 different combinations of 3 different color blink sequences per cluster location, thus totaling 18 types of spatial temporal signals. Moreover, repeated measurements showed good immunity to noise. The standard deviation of the measured results between each repetition was less than 5 mV.

Power-Efficient Thermal Optical Tunable Grating Coupler Based on Silicon Photonic Platform

A tunable grating coupler capable of dynamically changing the central wavelength with low power consumption is demonstrated and fabricated using a standard complementary metal–oxide–semiconductor process. The grating coupler is based on an efficient thermal tuning scheme employing free-standing silicon-on-insulator strip waveguides. The air gap provides thermal isolation between the heated grating structure and the underlying silicon substrate, which greatly enhance the heating efficiency. We achieve a thermal shift of 55 nm for the central wavelength with 19.5 mW and a record tuning efficiency of 2.82 nm/mW, which is more than one order of magnitude better than the previous demonstration. The measured rise time and fall time are 0.16 and 0.74 ms, respectively.

An Efficient Forward-Biased Si CMOS LED With High Optical Power Density and Nonlinear Optical-Power-Current Characteristic

A forward-biased silicon-based light-emitting device (Si-LED) was designed and fabricated by standard 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology without any modification. For the Si-LED, wedge-shaped electrodes and needle-like tip were designed to enhance the intensity of electric field. When the Si-LED works at high forward current, the output optical power increases rapidly with the increase of forward current, which is a non-linear growth similar to exponential. To the best of our knowledge, such a phenomenon has never been reported before. Moreover, when the forward current is at 200 mA, the optical power density reaches 32.7 nW·μm 2 , which is two or three orders higher than that of other ever reported forward-biased Si-LED fabricated by standard CMOS technology. In addition, the red shift of the main peak in the spectra of Si-LED was observed and analyzed, and also the light-emission mechanism of each peak in the spectra was given.

Inductive Micro Tri-Axial Tactile Sensor Using a CMOS Chip With a Coil Array

This letter presents a simple approach to implement the inductive-type micro tri-axial tactile sensor by integrating a complementary metal–oxide–semiconductor (CMOS) chip with sensing coils and a stainless steel sheet (as the sensing interface) using polymer encapsulation. In addition to the component integration, the polymer layer is exploited as the spring for the tactile sensor. The proposed CMOS-MEMS inductive tri-axial tactile sensor presents several features and advantages as follows: 1) the gap-closing inductive sensing approach is used for normal force ( ${Z}$ -axis) detection; 2) the area-change inductive sensing method is adopted for shear forces’ ( ${X}$ -axis and ${Y}$ -axis) detection; 3) the compact sensing coil array is implemented using the standard CMOS process; and 4) the polymer is employed as the encapsulation layer to cover and integrate the rigid stainless steel sheet sensing interface and the CMOS chip, while also acting as the spring to avoid the fragile suspended thin-film structure. To demonstrate the concept, a CMOS sensing chip with a $2\times 2$ coil array is fabricated using the Taiwan Semiconductor Manufacturing Company standard process and is further integrated with a stainless steel sheet prepared by laser machining. The measurements indicate that the typical fabricated tri-axial inductive tactile sensor exhibits a normal load sensitivity ( ${Z}$ -axis) of 2.9 nH/N, an ${X}$ -axis shear force sensitivity of 17.4 nH/N, and a ${Y}$ -axis shear force sensitivity of 15.3 nH/N.

A design of ± 0.28 ppm temperature-compensated crystal oscillator in a 0.35 μm CMOS process

A high-performance temperature-compensated crystal oscillator (TCXO) is presented. This paper proposes a new temperature sensor with a Σ–Δ analog to digital converter, and a voltage-controlled crystal oscillator, respectively, using two sets of independent power supply. The presented TCXO is implemented in a 0.35 μm 2P3 M standard complementary metal-oxide semiconductor process at a power supply of 3.3 V, and the total power dissipation is 21 mW. Measurement results indicate that the designed TCXO achieves ± 16 ppm output frequency tuning range and 135, − 141 dBc/Hz phase noise at 1, 10 kHz frequency offset, respectively, by using a 40 MHz fundamental AT-cut crystal resonator. With the temperature compensation, the frequency deviation is within ± 0.28 ppm over − 40 °C to 85 °C.

Deep Submicron EGFET Based on Transistor Association Technique for Chemical Sensing.

Extended-gate field-effect transistor (EGFET) is an electronic interface originally developed as a substitute for an ion-sensitive field-effect transistor (ISFET). Although the literature shows that commercial off-the-shelf components are widely used for biosensor fabrication, studies on electronic interfaces are still scarce (e.g., noise processes, scaling). Therefore, the incorporation of a custom EGFET can lead to biosensors with optimized performance. In this paper, the design and characterization of a transistor association (TA)-based EGFET was investigated. Prototypes were manufactured using a 130 nm standard complementary metal-oxide semiconductor (CMOS) process and compared with devices presented in recent literature. A DC equivalence with the counterpart involving a single equivalent transistor was observed. Experimental results showed a power consumption of 24.99 mW at 1.2 V supply voltage with a minimum die area of 0.685 × 1.2 mm2. The higher aspect ratio devices required a proportionally increased die area and power consumption. Conversely, the input-referred noise showed an opposite trend with a minimum of 176.4 nVrms over the 0.1 to 10 Hz frequency band for a higher aspect ratio. EGFET as a pH sensor presented further validation of the design with an average voltage sensitivity of 50.3 mV/pH, a maximum current sensitivity of 15.71 mA1/2/pH, a linearity higher than 99.9%, and the possibility of operating at a lower noise level with a compact design and a low complexity.

Reinforcement learning with analogue memristor arrays

Reinforcement learning algorithms that use deep neural networks are a promising approach for the development of machines that can acquire knowledge and solve problems without human input or supervision. At present, however, these algorithms are implemented in software running on relatively standard complementary metal–oxide–semiconductor digital platforms, where performance will be constrained by the limits of Moore’s law and von Neumann architecture. Here, we report an experimental demonstration of reinforcement learning on a three-layer 1-transistor 1-memristor (1T1R) network using a modified learning algorithm tailored for our hybrid analogue–digital platform. To illustrate the capabilities of our approach in robust in situ training without the need for a model, we performed two classic control problems: the cart–pole and mountain car simulations. We also show that, compared with conventional digital systems in real-world reinforcement learning tasks, our hybrid analogue–digital computing system has the potential to achieve a significant boost in speed and energy efficiency. A reinforcement learning algorithm can be implemented on a hybrid analogue–digital platform based on memristive arrays for parallel and energy-efficient in situ training.

Design and Simulation Study of Active Baluns Circuits for WiMAX Applications

The paper presents a design and simulation study of three active balun circuits implemented in a standard 90nm Complementary Metal-Oxide Semiconductor (CMOS) process namely: (1) common-source/drain active balun; (2) common-gate with common-source active balun; and (3) differential active balun. The active balun designs are intended for Worldwide Interoperability for Microwave Access (WiMAX) applications operating at frequency 5.8GHz and with supply voltage of 1V. Measurements are taken for parameters such as gain difference, phase difference, and noise figure. All designs achieved gain difference of less than 0.23dB, phase difference of 180° ± 7.1°, and noise figure of 7.2–9.85dB, which are comparable to previous designs and researches. Low power consumption attained at the most 4.45mW.

A dependency of emission efficiency of poly-silicon light-emitting device on avalanching current

A novel polysilicon light emitting device (LED) was realized in a standard complementary metal oxide semiconductor (CMOS) process that is based on a p-n junction reverse bias configuration. This LED can emit visible light based on the reverse bias p-n junctions in the dark. The central emitting doped structure element of this LED is n+-p-n+-p-n+ stacked layout, which is similar to two reverse bias p-n junctions and two forward bias p-n junctions connected in series. The device mechanism for the visible light emitting process is defined by means of an avalanche breakdown process that occurs between the highly doped n+ region and the lightly doped p region in the reverse bias p-n junctions. By using hot carriers generated in avalanche process, the emission spectrum from the device exhibits a wide spectrum whose wavelength range is from 400 nm to 900 nm at an operating voltage of 16 V. We compare the designed light intensities at the different wavelengths in other to obtain the dependency of the light emission at various wavelengths under different currents conditions. From the experimental observations, and based on the calculation of the quantum efficiency and power conversion efficiencies as related to the light emission, we confirmed that this particular LED has a better efficiency than three-terminal gated diode. The silicon light source could find some applications in on-chip optical interconnect and in electro-optical conversions in future all-silicon integrated photonic circuitry.

Silicon Photomultipliers With Area Up to 9 mm2 in a 0.35-$\mu$ m CMOS Process

Silicon photomultipliers produced using standard complementary metal oxide semiconductor (CMOS) processes are at the basis of modern applications of sensors for weak photon fluxes. They allow in fact to integrate transistor-based electronic components within sensors and provide intelligent read-out strategies. In this paper, we investigate the scalability of a 0.35- $\mu$ m CMOS process to large area devices. We report the design and characterization of SiPMs with a total area of 1, 4, and 9 mm2. Cross talk, photon detection efficiency at 420 nm, gain at 2.5 V overvoltage and breakdown voltage temperature coefficient do not depend on the total area of the sensor and are 10%, 35%, $2.5 \times 10^{6}$ , and and 35 mV/K, respectively. The dark count rate scales with the total area of the device as 180 kHz/mm2 The total output capacitance, the decay time of the single photon signal, and the single photon time resolution depend on the area of the device. We obtain a capacitance of 66.9, 270.2, and 554.0 pF, a decay time of (27.1±0.1) ns, (50.8±0.1) ns, and (78.2±0.1) ns and a single photon time resolution of (77.97±0.51) ps, (201.67 ± 0.98) ps, and (282.28 ± 0.86) ps for the 1, 4, and 9 mm2 SiPMs, respectively.

Application prospect of metal-oxide-semiconductor silicon light emitting devices in integrated circuits

Photonic interconnects have potentials to break increasingly severe energy efficiency and bandwidth density bottlenecks of electrical interconnect in scaled complementary metal oxide semiconductor (CMOS) integrated circuits, leading to the emergence of optoelectronic integrated circuits (OEICs) that utilize electronic and photonic devices together in a synergistic way to achieve better performance than those based on pure electronic device technology. By reviewing the progresses of Si-based light-emitting device, the schematic of MOS-like light source integrated with waveguides and the following photodetector is analyzed for its availability. It is believed that on-chip optical interconnects could be achieved by standard CMOS technology successfully with the speed as fast as the velocity of light, supplying propulsions for nest-generation OEICs.

Improved Performance of CMOS Terahertz Detectors by Reducing MOSFET Parasitic Capacitance

The parasitic circuit elements significantly affect rectification performance of metal-oxide-semiconductor field-effect transistor devices. In this paper, we develop a gate-source parasitic capacitance reduction technique by shifting the source lightly doped drain region and analyze the effectiveness on the improved performance of complementary metal-oxide-semiconductor (CMOS) terahertz (THz) detectors. It is experimentally found that for a 0.65-THz integrated CMOS detector, the maximum improvement of voltage responsivity and noise-equivalent power can be 155% and 70%, respectively, by suppressing the gate-source parasitic capacitance. The device simulation further quantitatively evaluates the gate-source parasitic capacitance under different gate-source overlap areas in the novel fabricated transistor structure. It reveals that a smaller gate-source overlap area can result in a lower gate-source parasitic capacitance, which is more favorable for reducing input THz signal leakage and therefore for increasing the THz responsivity. The works open a wide range of possibilities for the ease of design and fabrication of the high-performance THz detectors in standard CMOS technology.

A Radiation-Hardened Instrumentation Amplifier for Sensor Readout Integrated Circuits in Nuclear Fusion Applications

A nuclear fusion reactor requires a radiation-hardened sensor readout integrated circuit (IC), whose operation should be tolerant against harsh radiation effects up to MGy or higher. This paper proposes radiation-hardening circuit design techniques for an instrumentation amplifier (IA), which is one of the most sensitive circuits in the sensor readout IC. The paper studied design considerations for choosing the IA topology for radiation environments and proposes a radiation-hardened IA structure with total-ionizing-dose (TID) effect monitoring and adaptive reference control functions. The radiation-hardened performance of the proposed IA was verified through model-based circuit simulations by using compact transistor models that reflected the TID effects into complementary metal–oxide–semiconductor (CMOS) parameters. The proposed IA was designed with the 65 nm standard CMOS process and provides adjustable voltage gain between 3 and 15, bandwidth up to 400 kHz, and power consumption of 34.6 μW, while maintaining a stable performance over TID effects up to 1 MGy.