Standard Complementary Metal Oxide Semiconductor Research Articles

ECONOMIC SIGNIFIANCE AND DESIGN OF LOW AREA AND LOW POWER MAGNITUDE COMPARATOR

Multibit digital comparators take up large surface and high power consumption. As they are composed of logic gates, it is recommended to decrease the number of transistors in the logic gates using different transistor logics. By decreasing the number of transistors, the occupied surface and power consumption of the entire circuit will also decrease. The identical circuit was propounded applying standard CMOS (Complementary MetalOxide-Semiconductor) technology and with a combination of PTL (Pass Transistor Logic) and DVL (Dual Value Logic) transistor logics. Due to less area and decreased number of transistors, the physical design (layout) of the whole circuit will become easier and less time consuming from layout designer point of view, then in case of standard CMOS technology. As an output load was used a 1fF capacitance for both circuits. Correspondingly, the propounded circuit cuts down the power consumption by 21.3%, the delay was decreased by 28.4%, and the number of transistors was reduced by 25%. The circuit was developed using Custom Compiler tool. All the simulations are done using Synopsys Hspice and WaveView tools. SAED (Synopsys Armenia Educational Department) 32/28 nm technology process libraries have been used during the work.

Design and fabrication of a high-performance binary blazed grating coupler for perfectly perpendicular coupling

A high-performance binary blazed grating coupler (BBGC) on a silicon-on-insulator (SOI) platform for perfectly vertical coupling has been proposed. The period and the etching depth of the grating and the fill factors of the sub-gratings are simulated optimally with manufacturable feature sizes, and the coupling efficiency (CE) is as high as −1.78 dB at 1550 nm with a broad 3-dB bandwidth of around 100 nm. Then, a BBGC with the CE of −3.69 dB at 1550.5 nm and a 3-dB bandwidth of about 70 nm was experimentally demonstrated. Moreover, a large process tolerance of about 20 nm on the narrower sub-grating width was proved, achieving the insertion loss lower than −4.64 dB at 1550 nm. The realization of the BBGC on a SOI platform is simple, repeatable, and compatible with standard complementary metal-oxide semiconductor (CMOS) technology.

A Logic Verification Framework for SFQ and AQFP Superconducting Circuits

Traditional logical equivalence checking (LEC), which plays a major role in the entire chip design process, faces challenges of meeting the requirements demanded by the many emerging technologies that are based on logic models different from the standard complementary metal oxide semiconductor (CMOS). In this article, we propose an LEC framework to be employed in the verification process of superconducting electronics (SCE). Our LEC framework is compatible with the existing CMOS technologies and can also check features and capabilities that are unique to SCE. For instance, the performance of nonresistively biased single-flux quantum (SFQ) circuits benefits from ultradeep pipelining, and verification of such circuits requires new models and algorithms. We, therefore, present the multicycle input dependency circuit model which is a novel model representation of design to explicitly capture the dependency of primary outputs of the circuit on sequences of internal signals and inputs. Embedding the proposed circuit model and several structural checking modules, the process of verification can be independent of the underlying technology and signaling. We benchmark the proposed framework on postsynthesis SFQ and 4-phase adiabatic quantum flux parametron netlists. Results show a comparative verification time of SFQ circuit benchmark, including 16-bit integer divider and ISCAS’85 circuits with respect to the ABC tool for similar CMOS circuits.

A comprehensive review of FET‐based pH sensors: materials, fabrication technologies, and modeling

AbstractThe demand for miniaturized point‐of‐care chemical/biochemical sensors has driven the development of field‐effect transistors (FETs) based pH sensors over the last 50 years. This paper aims to review the fabrication technologies, device structures, sensing film materials, and modeling techniques utilized for FET‐based pH sensors. We present the governing principles of potentiometric sensors, with major focus on the working principles of ion‐sensitive FETs (ISFETs). We extensively review different sensing film materials deposited by various techniques, which is critical to the sensing performance of ISFETs. The popular fabrication technologies have been presented, with special emphasis on state‐of‐the‐art silicon‐on‐insulator based technology, which can achieve high sensitivity by utilizing the dual‐gate effect. Furthermore, recent advancements in nano‐ISFETs has been elucidated. We also discuss the adoption of unmodified complementary metal‐oxide semiconductor (CMOS) ISFETs using standard CMOS processes, which has enabled the fabrication of integrated ISFET arrays, which are especially suited for ion‐imaging applications. Moreover, recent developments in extended‐gate FETs has been discussed, which have gained lot of attention due to their design flexibility and ease of fabrication, which is desirable for wearable sensing applications. In addition, recently there have been efforts to utilize nonsilicon channel materials for pH‐sensing application to obtain superior performance and various channel materials have been reviewed. Finally, we have extensively reviewed the ISFET device modeling and simulation techniques using various computer‐aided design tools, which aid in sensor design and characterization.

Alternative material titanium nitride based refractive index sensor embedded with defects: An emerging solution in sensing arena

This article presents an ultra-compact refractive index sensor based on titanium nitride (TiN), a well-known alternative plasmonic material. The designed sensor consists of a straight waveguide, coupled with a groove and a Square-Ring Resonator (SRR). In addition, nanosized TiN dots are embedded in the waveguide and groove to enhance sensing performance. The spectral characteristics of the proposed sensor are numerically analyzed using the Finite Element Method (FEM). After extensive simulations, the most optimal structure provides a maximum sensitivity of 1074.88 nm/RIU and a Figure of Merit (FOM) of 32.4 and proves to be tolerant against probable real-life manufacturing defects. Furthermore, the incorporation of TiN equips the illustrated sensor with numerous advantages, for example, immunity to oxidation, optical tunability, capability to endure high-temperature, and compatibility with the standard Complementary Metal Oxide Semiconductor (CMOS) fabrication process. The major pitfall of traditional plasmonic metals is that the metals lack all these qualities, limiting real-life implementations of plasmonic devices. Therefore, the proposed model is superior to the conventional Metal–Insulator–Metal (MIM) setup and is expected to facilitate the development of practical, robust sensors.

Folded 15-channel arrayed waveguide gratings on silicon nitride platform with loop reflector

Silicon nitride (Si3N4) arrayed waveguide gratings (AWGs) have been widely used for dense wavelength division multiplexing systems because of their low loss and crosstalk. However, they have larger footprints because of their lower relative index compared with silicon-on-insulator (SOI) devices. In this study, a folded 1×15 Si3N4 AWG was fabricated on an SOI wafer with a silicon photonics loop reflector. The combination of the Si3N4 AWG and the Si loop reflector greatly reduced the device footprint and increased the fabrication tolerances. A layer coupler was used to connect the arrayed waveguides of the AWG to the Si loop reflector. The folded AWG consisted of a half Si3N4 AWG structure, an layer coupler array, and a Si loop reflector array. The measured insertion loss and crosstalk of the designed AWG were -5.46 dB and -17.2 dB, respectively. The integration of the half Si3N4 AWG and the arrayed Si loop reflectors can effectively reduce the large footprint of a Si3N4 AWG device with a standard complementary metal–oxide–semiconductor process while maintaining a relatively high performance.

Circuit Level Realization of Low Latency Radix-4 Booth Scheme for Parallel Multipliers

A novel radix-4 Booth encoding scheme has been presented in this paper. By means of the modified truth table, the transistor level delay from inputs to the partial products has been reduced to four transistors. Also, the output waveforms are free of glitch due to the utilization of pass-transistor logic. The calculation of propagation delay for the critical path has been provided to show the superior speed performance of the proposed architecture. Based on the simulation results using HSPICE for Taiwan semiconductor manufacturing company 0.18 µm standard complementary metal–oxide–semiconductor process and 1.8 V power supply, a speed improvement of 24% is obtained compared to the previous architectures when the proposed scheme along with the best reported works have been redesigned and simulated in the same technology platform.

High-Speed DD Transmission Using a Silicon Receiver Co-Integrated With a 28-nm CMOS Gain-Tunable Fully-Differential TIA

We report >100-Gb/s direct-detection (DD) transmission using an integrated silicon optical receiver, which comprised a fully-differential 28-nm complementary metal-oxide-semiconductor (CMOS) transimpedance amplifier (TIA) wire-bonded to a Silicon-Germanium (SiGe) balanced photodiode (PD). The fully-differential TIA architecture enabled significant bit-error-rate (BER) and signal-to-noise ratio improvements over a single-output TIA design when introducing it to the DD transmission. We experimentally validated its effectiveness in both back-to-back (B2B) and 2-km long standard single-mode fibre (SSMF) links using 50/100-Gb/s signals, including Nyquist on-off keying (OOK), Nyquist 4-ary pulse amplitude modulation (PAM4), uniformly-loaded DD optical orthogonal frequency division multiplexing (DDO-OFDM) and adaptively-loaded DDO-OFDM. Furthermore, we demonstrate that the integrated optical receiver was capable of balancing the trade-off between its electrical bandwidth and transimpedance gain by simply adjusting a voltage supply to the TIA. Without the need for optical amplification and while keeping the BERs below the 7% forward error correction limit, up to 173.22-Gb/s and 139.86-Gb/s adaptively-loaded DDO-OFDM transmission was achieved for B2B and 2-km transmission, respectively. The demonstrated results highlight the potential of the integrated silicon optical receiver, fabricated using the standard CMOS process for high-speed and short-reach optical interconnects.

Energy efficient neural stimulator with dynamic supply modulation

This paper reports an automatically reconfigurable series–parallel switched-capacitor step-down DC–DC converter for neural stimulation applications, fabricated with a 0.13 μm standard complementary metal oxide semiconductor process. The stimulator chip can generate pre-programmed biphasic or dynamically programmed arbitrary current waveforms, up to ±127 μA peak with 7-bit resolution. To improve the power efficiency, the supply voltages of the stimulating current sources are dynamically modulated following the output voltage. The functionality of the stimulator is verified in vitro using parylene-based microelectrode arrays in phosphate-buffered saline.

Broadband and compact silicon mode converter designed using a wavefront matching method.

A broadband and compact TE0-TE1 mode converter for a mode division multiplexing system designed using a wavefront matching method is realized. We present the first experimental demonstration of a silicon waveguide device designed by a wavefront matching method. In order to achieve broadband operation of the silicon mode converter, seven wavelengths are considered in its optimization process. The designed silicon mode converter is fabricated via a standard complementary metal-oxide-semiconductor technology, which enables low-cost mass production. Measurements performed using the fabricated mode converter correlate strongly with the calculated results.

Homogeneous 3D Vertical Integration of Parylene‐C Based Organic Flexible Resistive Memory on Standard CMOS Platform

Abstract3D integration of vertical resistive random access memory (VRRAM) with organic materials is promising for ultra‐high density flexible data storage. However, it is extremely challenging to heterogeneously fabricate an organic 3D VRRAM due to complicated issues such as chemical/thermal robustness, compatibility of organic/inorganic materials, and processes of stacking/patterning multi‐layer organic/metal films. Herein, an organic flexible 3D VRRAM based on parylene‐C is experimentally demonstrated on a standard complementary metal oxide semiconductor platform for the first time. The proposed 3D VRRAM can be homogenously fabricated based solely on parylene‐C (except the metal electrodes), significantly facilitating the 3D integration owing to chemical stability and compatibility with standard photolithography patterning. The flexible 3D organic memory arrays demonstrate great memory characteristics including retention time >105 s, endurance cycles >300, and resistance ON/OFF ratio >10. Further, a finite element analysis is established to model and investigate the scaling potential of the organic 3D VRRAM. The simulation results indicate the elevated temperature during programming could be catastrophic for ultra‐high density 3D VRRAM if the feature size approaches ≈100 nm or below, urging the containment of programming power to avoid thermal issues as well as to save energy consumption.

A CMOS-MEMS BEOL 2-axis Lorentz-Force Magnetometer with Device-Level Offset Cancellation.

Lorentz-force Microelectromechanical Systems (MEMS) magnetometers have been proposed as a replacement for magnetometers currently used in consumer electronics market. Being MEMS devices, they can be manufactured in the same die as accelerometers and gyroscopes, greatly reducing current solutions volume and costs. However, they still present low sensitivities and large offsets that hinder their performance. In this article, a 2-axis out-of-plane, lateral field sensing, CMOS-MEMS magnetometer designed using the Back-End-Of-Line (BEOL) metal and oxide layers of a standard CMOS (Complementary Metal–Oxide–Semiconductor) process is proposed. As a result, its integration in the same die area, side-by-side, not only with other MEMS devices, but with the readout electronics is possible. A shielding structure is proposed that cancels out the offset frequently reported in this kind of sensors. Full-wafer device characterization has been performed, which provides valuable information on device yield and performance. The proposed device has a minimum yield of with a good uniformity of the resonance frequency kHz, kHz and quality factor , at ambient pressure. Device sensitivity to magnetic field is fAT at Pa when driven with .

A new optical random number generator circuit design using single-photon avalanche diodes

In this paper a new optical random number generator circuit is presented and post layout simulated in 180 nm standard Complementary Metal Oxide Semiconductor (CMOS) technology. The random nature of the photon population detected in a fixed time interval is used as the entropy source to generate two bit random numbers. In the proposed circuit three single photon avalanche diodes (SPADs) are organized in parallel to detect photons. Each time, a single SPAD among the three is biased in Geiger mode and the other two SPADs are in the hold off phase, to reduce dark count rate and afterpulsing. A SPAD circuit model is used to verify the circuit functionality. The energy consumption per bit of 16pj/bit and the generation rate of 80 MHz are obtained. To evaluate the performance of the proposed system, statistical tests of NIST (National Institute of Standards and Technology) are applied to 1Gbit generated data using numerical simulations and all the randomness tests are passed successfully.

Low-Cost Microbolometer Type Infrared Detectors

The complementary metal oxide semiconductor (CMOS) microbolometer technology provides a low-cost approach for the long-wave infrared (LWIR) imaging applications. The fabrication of the CMOS-compatible microbolometer infrared focal plane arrays (IRFPAs) is based on the combination of the standard CMOS process and simple post-CMOS micro-electro-mechanical system (MEMS) process. With the technological development, the performance of the commercialized CMOS-compatible microbolometers shows only a small gap with that of the mainstream ones. This paper reviews the basics and recent advances of the CMOS-compatible microbolometer IRFPAs in the aspects of the pixel structure, the read-out integrated circuit (ROIC), the focal plane array, and the vacuum packaging.

From Charge to Spin and Spin to Charge: Stochastic Magnets for Probabilistic Switching

As the rapid pace of Moore's Law has been slowing down, there has been intense activity to “reinvent the transistor.” An emerging paradigm is to complement the existing complementary metal-oxide-semiconductor (CMOS) technology with new functionalities, rather than finding a drop-in replacement for it. In this article, we discuss such a complementary approach that we call probabilistic spin logic (PSL) based on the concept of a probabilistic or p-bit. p-bits fluctuate between 0 and 1 and can be imagined in between deterministic bits that are either 0 or 1 and quantum bits that are a superposition of 0 and 1. Interconnected circuits built out of p-bits (p-circuits) can be broadly useful for machine learning and quantum computing in the solution of problems that conventional CMOS may not be particularly suited for. Although such p-bits can be implemented using standard CMOS technology, we will show that the inherent physics of nanomagnets can naturally provide an energy efficient and scalable p-bit implementation through the use of low-barrier magnetic tunnel junctions (MTJs). In this article, we provide a general description of p-bits and p-circuits and discuss their applications. We review experimental progress toward constructing p-bits and p-circuits exploiting the inherent stochasticity of nanomagnets, from a physics/device/circuits perspective. In particular, we identify building blocks for “write” and “read” operations that can be used in different combinations to construct functional p-bits and p-circuits. Finally, we discuss the prospects and challenges of PSL as an emerging, unconventional computing paradigm for a beyond CMOS era.

Broadband high-efficiency triple-tip spot size converter for edge coupling with improved polarization insensitivity

Fiber-to-chip couplers are an essential part of the interfaces to integrated photonic devices, and high coupling efficiency over a broad wavelength range is preferred for most applications. Furthermore, couplers with low polarization dependence are also of great practical significance. While tapered waveguide couplers have been applied to overcome the mode mismatch between waveguides and fibers, the inherent geometric asymmetry of high-index-contrast waveguides, especially for those with a thick core layer, leads to polarization dependence in their performance. Here a triple-tip spot size converter as an edge coupler is proposed to improve the polarization insensitivity and coupling efficiency over a broadband range for either thick or thin waveguides. For both TE and TM polarization, it is shown that our design can have below 1 dB coupling loss over a 600 nm window around 1550 nm wavelength for Si3N4 waveguides of typical core thicknesses. Meanwhile, this kind of coupler also shows better fabrication and assembly tolerance than the traditional single-tip spot size converter (inverse taper coupler). Our proposed device can be easily fabricated in simple fabrication processes compared to other designs and have good compatibility with the standard complementary metal-oxide–semiconductor processes.

A 108 F2/Bit Fully Reconfigurable RRAM PUF Based on Truly Random Dynamic Entropy of Jitter Noise

In this paper, we present a fully reconfigurable resistive random access memory (RRAM) physical unclonable function (PUF) based on the truly random dynamic entropy of the ubiquitous jitter noise, which is intrinsically different from most previously demonstrated PUF implementations with semiconductor fabrication’s process variation as the static entropy source. In addition, the proposed RRAM PUF is operated by configuring the mainstream RRAM cells to either high resistance state (for ‘1’) or low resistance state (for ‘0’), according to the customized ring oscillator (RO) true random number generator’s digital output that is determined by the random jitter noise. By completely removing the need of dedicated split resistance circuitry (SRC) in existing RRAM PUFs, the proposed implementation is fully compatible with the SET/RESET operations of the RRAM array for mainstream memory applications, leading to minimized design overhead and enhanced reliability without SRC-caused error bits. Fabricated using 130 nm standard complementary-metal-oxide-semiconductor (CMOS) process plus post-processing dedicated to the RRAM devices, the proposed RRAM PUF cell features an ultra-compact footprint of $1.82~\mu \text{m}^{2}$ (i.e., 108 $F^{2}$ ), which is capable of generating ~107 PUF bits per cell due to the time-variant property of jitter noise and the full reconfigurability of the RRAM PUF. This significantly innovates all the previous weak PUF implementations based on the static entropy source of process variation, where the maximum bit number per PUF cell is always limited and fixed after the chip fabrication. Meanwhile, ultra-low native unstable bits of 0.28% and bit error rate (BER) per 10°C of 0.03% can be achieved for the fabricated RRAM PUF. Moreover, by passing the widely-adopted bias test, National Institute of Standards and Technology (NIST) test and autocorrelation function (ACF) test under various VT conditions, the true randomness of the customized RO TRNG’ dynamic entropy is validated using 65 nm standard CMOS process. Compared with the state-of-the-art weak PUF implementations, the native unstable bits is improved by $5.36\times $ and the BER per 10°C is improved by $4\times $ , even under the widest operating temperature range from −50°C to 150°C.

Recent Progress of Soft Electrothermal Actuators.

Developing soft electrothermal actuators (ETAs) has drawn extensive concern in recent years. This article presents a comprehensive review on recent progress of soft ETAs through five sections: device design on structure and materials, property, fabrication methods, applications, and prospects. It's found that the fabrication process can be divided into standard surface complementary metal oxide semiconductor technology, novel laser scribing, and inkjet printing method. Moreover, current applications involve three aspects: mechanical applications, optical applications, and biomimetic applications. It will develop in the direction of increasing electrothermal efficiency and response speed emphatically. This review encourages achievement of its higher performance and broad applications in the future.

Easily reproducible top-emitting organic light-emitting devices for microdisplays adapted to aluminum contact from the standard CMOS processes

Organic light-emitting devices (OLEDs) on the silicon backplanes processed via the standard foundry complementary metal–oxide-semiconductor (CMOS) processes were developed with the state-of-the-art electrical doping technology to meet the optical and electrical requirements, resulting in high luminance (over 5000 cd/m2) for the green emissive OLED microdisplay. The unavoidable oxidized aluminium contact after the CMOS processes on the top layer of the pixel was found to significantly increase the driving voltage of the device (up to 1 V at 100 cd/m2 luminance). To aid in the extraction of the accurate device parameters for setting up an equivalent circuit, the reference top-emitting OLEDs without bottom metal contacts were deposited directly on interconnection-metal-only silicon substrates from the CMOS foundry. The distribution of the AlOx of the top-layer metal contact on silicon (the bottom anode of OLEDs) was confirmed by the X-ray photoelectron spectroscopy (XPS) depth profiles.

Fabrication and Electrical Characterization of Ultra-Thin Body and BOX (UTBB) Back Enhanced SOI (BESOI) pMOSFET

This work analyzes the third generation BESOI MOSFET (Back-Enhanced Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect-transistor) built on UTBB (Ultra-Thin Body and Buried Oxide), comparing it to the BESOI with thick buried oxide (first generation). The stronger coupling between front and back interfaces of the UTBB BESOI device improves in 67% the current drive, 122% the maximum transconductance and 223% the body factor. Operating with seven times lower back gate bias, the UTBB BESOI MOSFET presented more compatibility with standard SOI CMOS (Complementary MOS) technology than the BESOI with thick buried oxide.