Standard Complementary Metal Oxide Semiconductor Research Articles

Ferroelectric Polarization Coupling Effect in BiFeO3/α‐In2Se3 Ferroelectric Field Effect Transistor for Stable Non‐volatile Memory

AbstractFerroelectric field‐effect transistors (FeFETs) commonly utilize traditional oxide ferroelectric materials for their strong remanent polarization. Yet, integrating them with the standard complementary metal oxide semiconductor (CMOS) process is challenging due to the need for lattice matching and the high‐temperature rapid thermal annealing process, which are not always compatible with CMOS fabrication. However, the advent of the ferroelectric semiconductor α‐In2Se3 offers a compelling solution to these challenges. Its van der Waals layered structure facilitates integration with dielectric oxides, bypassing the lattice mismatch problem. Moreover, the ferroelectric polarization of α‐In2Se3 synergizes with the polarization of the ferroelectric dielectric layer. This coupling effect significantly enhances the polarization retention and the data storage capabilities of FeFETs. Here, a dual FeFET is designed that incorporates a BiFeO3 dielectric layer and an α‐In2Se3 channel, showing an improvement in performance compared to FeFETs that use MoS2 as the channel material with a BiFeO3 dielectric, or those with an α‐In2Se3 channel and a HfO2 dielectric. The dual FeFET exhibits an extended retention time of up to 1000 s at 380 K. Though there is still room for further improvement in data retention capabilities, this achievement paves the way for advancements in non‐volatile memory technologies.

Ultrasensitive integrated circuit sensors based on high-order non-Hermitian topological physics.

High-precision sensors are of fundamental importance in modern society and technology. Although numerous sensors have been developed, obtaining sensors with higher levels of sensitivity and stronger robustness has always been expected. Here, we propose theoretically and demonstrate experimentally an alternative class of sensors with superior performances based on exotic properties of high-order non-Hermitian topological physics. The frequency shift induced by perturbations for these sensors can show an exponential growth with respect to the size of the device, which can grow well beyond the limitations of conventional sensors. The fully integrated circuit chips have been designed and fabricated in a standard 65-nanometer complementary metal-oxide semiconductor process technology. Not only has the sensitivity of systems less than 10-3 femtofarad been experimentally verified, but these systems are also robust against disorders. Our proposed ultrasensitive integrated circuit sensors can have a wide range of applications in various fields and show an exciting prospect for next-generation sensing technologies.

Biocompatibility characterisation of CMOS-based Lab-on-Chip electrochemical sensors for in vitro cancer cell culture applications

Lab-on-Chip electrochemical sensors, such as Ion-Sensitive Field-Effect Transistors (ISFETs), are being developed for use in point-of-care diagnostics, such as pH detection of tumour microenvironments, due to their integration with standard Complementary Metal Oxide Semiconductor (CMOS) technology. With this approach, the passivation of the CMOS process is used as a sensing layer to minimise post-processing, and Silicon Nitride (Si3N4) is the most common material at the microchip surface. ISFETs have the potential to be used for cell-based assays however, there is a poor understanding of the biocompatibility of microchip surfaces. Here, we quantitatively evaluated cell adhesion, morphogenesis, proliferation and mechano-responsiveness of both normal and cancer cells cultured on a Si3N4, sensor surface. We demonstrate that both normal and cancer cell adhesion decreased on Si3N4. Activation of the mechano-responsive transcription regulators, YAP/TAZ, are significantly decreased in cancer cells on Si3N4 in comparison to standard cell culture plastic, whilst proliferation marker, Ki67, expression markedly increased. Non-tumorigenic cells on chip showed less sensitivity to culture on Si3N4 than cancer cells. Treatment with extracellular matrix components increased cell adhesion in normal and cancer cell cultures, surpassing the adhesiveness of plastic alone. Moreover, poly-l-ornithine and laminin treatment restored YAP/TAZ levels in both non-tumorigenic and cancer cells to levels comparable to those observed on plastic. Thus, engineering the electrochemical sensor surface with treatments will provide a more physiologically relevant environment for future cell-based assay development on chip.

Epitaxial Growth of Large-Scale 2D CrTe2 Films on Amorphous Silicon Wafers With Low Thermal Budget.

2D van der Waals (vdW) magnets open landmark horizons in the development of innovative spintronic device architectures. However, their fabrication with large scale poses challenges due to high synthesis temperatures (>500 °C) and difficulties in integrating them with standard complementary metal-oxide semiconductor (CMOS) technology on amorphous substrates such as silicon oxide (SiO2) and silicon nitride (SiNx). Here, a seeded growth technique for crystallizing CrTe2 films on amorphous SiNx/Si and SiO2/Si substrates with a low thermal budget is presented. This fabrication process optimizes large-scale, granular atomic layers on amorphous substrates, yielding a substantial coercivity of 11.5 kilo-oersted, attributed to weak intergranular exchange coupling. Field-driven Néel-type stripe domain dynamics explain the amplified coercivity. Moreover, the granular CrTe2 devices on Si wafers display significantly enhanced magnetoresistance, more than doubling that of single-crystalline counterparts. Current-assisted magnetization switching, enabled by a substantial spin-orbit torque with a large spin Hall angle (85) and spin Hall conductivity (1.02 × 107 ℏ/2e Ω⁻¹ m⁻¹), is also demonstrated. These observations underscore the proficiency in manipulating crystallinity within integrated 2D magnetic films on Si wafers, paving the way for large-scale batch manufacturing of practical magnetoelectronic and spintronic devices, heralding a new era of technological innovation.

Stepped-Tube Backside Cavity Piezoelectric Ultrasound Transducer Based on Sc0.2AI0.8N Thin Films.

This paper presents a novel piezoelectric micromachined ultrasonic transducer (PMUT) with theoretical simulation, fabrication, and testing. Conventional methods using a PCB or an external horn to adjust the PMUT acoustic field angle are limited by the need for transducer size. To address this limitation, the stepped-tube (expanded tube) backside cavity PMUT has been proposed. The stepped-tube PMUT and the tube PMUT devices have the same membrane structure, and the acoustic impedance matching of the PMUT is optimized by modifying the boundary conditions of the back cavity structure. The acoustic comparison experiments show that the average output sound pressure of the stepped-tube backside cavity PMUT has increased by 17%, the half-power-beam-width (θ-3db) has been reduced from 55° to 30° with a reduction of 45%, and the side lobe level signal is reduced from 147 mV to 66 mV. In addition, this work is fabricated on an eight-inch wafer. The process is compatible with standard complementary metal oxide semiconductor (CMOS), conditions are stable, and the cost is controllable, plus it facilitates the batch process. These conclusions suggest that the stepped-tube backside cavity PMUT will bring new, effective, and reliable solutions to ranging applications.

Exploring the impact of domain numbers on negative capacitance effects in ferroelectric Device-Circuit Co-Design

This paper explores the performance of Hf0.5Zr0.5O2 (HZO)-stacked negative capacitance field-effect transistor (NCFET) for possible beyond complementary metal–oxide–semiconductor (CMOS) technology. For the first time, we investigate the impact of ferroelectric (FE) domain numbers on the negative capacitance (NC) effect, energy dissipation, NC effect voltage window, polarization ramping rate, voltage amplification (ANC), and oscillation frequency of a 5-stage HZO-NCFET inverter-based ring oscillator (HZO-NCFET-RO). The results show that HZO-NCFET is suitable for low-voltage and high-speed applications, providing a significant increase in ANC concerning the conventional PZT-NCFET and P(VDF-TrFE)-NCFET. Our study suggests that the HZO intrinsic NC effect time scale is tiny and limited by the FE switching. We show that the switching time of HZO is ∼20 times faster than the traditional FE [Pb(Nb0.04Zr0.28Ti0.68)O3]. Finally, the proposed 5-stage HZO-NCFET-RO offers superior performance with a 26% higher oscillation frequency and a 94.42% reduction in power dissipation compared to standard 5-stage CMOS inverter-based RO. These findings highlight the potential of HZO-stacked NCFET as an alternative device for the future beyond-CMOS technology.

Enhancing photodetection efficiency of CMOS SiPMs using virtual guard rings in a standard 0.35 µm process

AbstractIn this letter, a design of virtual guarded SiPMs fabricated in a standard 0.35μm standard complementary metal oxide semiconductor (CMOS) process is introduced. The performance of these virtual guarded cells (VGC) is compared to that of conventional cells with real guard rings, referred to as physical guarded cells (PGC). Specifically, the photon detection efficiency (PDE) of both types of SiPMs is evaluated. For this, PDE calculations are conducted at different overvoltages (OVs) and the PDE is compared depending on the wavelength before conducting measurements. The results demonstrate that the VGC SiPM outperforms the PGC SiPM, exhibiting a true PDE of (22.5 ± 0.5)%, which is significantly higher than the PDE of (10.9 ± 0.3)% obtained for the PGC SiPM. The superior PDE of the VGC SiPM is attributed to a larger active or photosensitive area due to the virtual guard rings and a thinner n‐layer in the photosensitive region.

Formal Verification of Sequential Circuits in Superconducting Single Flux Quantum Technologies

Logical equivalence checking is one of the most effective verification steps in the entire design process of integrated circuits. However, it faces challenges in emerging technologies due to differences between its logic models and those of the standard complementary metal oxide semiconductor (CMOS). This paper presents qSC, an equivalence checking framework targeting <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sequential</i> circuits mapped to rapid superconducting single-flux-quantum (RSFQ) logic circuits. In addition to a logical checking module, qSC also includes several structural checking modules. The structural checking modules are used to check whether the circuit meets the design rules of superconducting RSFQ logic circuits. The main difficulty of verifying nonlinear <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sequential</i> circuits is in finding the levels of logic cells in the circuit for full-path-balancing checking for which the conventional topological sorting algorithm of acyclic digraphs is not applicable. The key is to define and calculate levels for nodes in a cyclic graph and to avoid any loop trap. Hence, a new algorithm is presented for full-path-balancing checking of the cyclic digraph that satisfies all of these desirable features. The experimental results show the feasibility of qSC on sequential circuits implemented in RSFQ technologies.

Long-infrared dual-wavelength linear-polarization-multiplexed confocal metalens based on an all-silicon dielectric.

The metalens has vast applications in biomedicine and industrial manufacturing due to their ultrathin structure and vital ability to manipulate the properties of light waves for long-infrared systems. However, it is difficult for metalens to achieve the confocal function with high focusing efficiency, wide wavelength bandwidth, and low structural complexity. Here, we propose and experimentally demonstrate an all-silicon dielectric metalens composed of arrays of minimalist meta-atoms with a single rectangular nanopillar arranged on a periodic square lattice substrate, which realizes the confocal function of the orthogonal-linear-polarized light with wavelengths of 10.6 µm and 9.3 µm, with focusing efficiencies of 64.94% and 60.03%, respectively. Also, it reveals nearly the diffraction-limited focusing performance. In addition, the metalens can realize precise long-infrared thermal imaging. Moreover, the proposed metalens is compatible with the standard complementary metal oxide semiconductor processes, which can effectively reduce the manufacturing cost and provide a feasible solution for developing planar integrated multifunctional micro-nanophotonic devices in the long-infrared field.

ZrN-based plasmonic sensor: a promising alternative to traditional noble metal-based sensors for CMOS-compatible and tunable optical properties.

In this article, we introduce a novel comb shaped plasmonic refractive index sensor that employs a ZrN-Insulator-ZrN configuration. The sensor is constructed using Zirconium Nitride (ZrN), an alternative refractory material that offers advantages over traditional metals such as silver and gold, as ZrN is standard Complementary Metal Oxide Semiconductor (CMOS)-compatible and has tunable optical properties. The sensor has recorded a maximum sensitivity, figure of merit (FOM), and sensing resolution of 1445.46 nm/RIU, 140.96, and 6.91 × 10-7RIU-1, respectively. Beyond that, the integration of ZrN offers the sensor with various advantages, including higher hardness, thermal stability at high temperatures, better corrosion and abrasion resistance, and lower electrical resistivity, whereas traditional plasmonic metals lack these properties, curtailing the real-world use of plasmonic devices. As a result, our suggested model surpasses the typical noble material based Metal-Insulator-Metal (MIM) arrangement and offers potential for the development of highly efficient, robust, and durable nanometric sensing devices which will create a bridge between nanoelectronics and plasmonics.

Room temperature-grown highly oriented p-type nanocrystalline tellurium thin-films transistors for large-scale CMOS circuits

Although facile fabrication of high-performance thin-film transistor (TFT)-based complementary metal oxide–semiconductor (CMOS) circuits over a large area has generated significant interest, the lack of reliable and uniform p-type TFTs is hindering it. In this study, we prepared high-performance CMOS circuits using room temperature deposited nanocrystalline tellurium (nc-Te) and sputtered amorphous-indium gallium zinc oxide (a-IGZO) TFTs. The facile polyethyleneimine (PEI) surface treatment enabled Te atom anchoring and crystal orientation control along with continuous surface coverage, resulting in a high-performance TFT with an average mobility of 21.1 cm2V−1s−1 and an Ion/Ioff ratio of 104. By introducing monolithic integration of nc-Te and a-IGZO TFTs, various CMOS circuits including inverter, NAND, and NOR circuits were fabricated and operated quite logically. Moreover, seven-stage ring oscillators comprising 14 cross-wired TFTs validated the cascading of multiple stages and device uniformity of the complementary system, achieving an oscillation frequency up to 392.16 kHz at VDD of 20 V. nc-Te on a PEI-treated surface offers a general route to producing high-performance and stable p-type semiconductors while ensuring compatibility with standard CMOS processing and large-scale on-chip device applications.

3D lithography enable ultrathin flat compound eye for moving object imaging

With a hemispherical surface, the compound eye cameras inspired by arthropod eyes provide a large field of view (FOV), low aberration, and a large depth of field. However, to match the hemisphere-imaging plane, the cameras require a hemisphere-photoelectric sensor instead of a standard planar complementary metal oxide semiconductor (CMOS) sensor. Additionally, the hemispheric shape of the imaging system restricts the miniaturization of high-performance compound eye cameras at the millimeter scale. Here, inspired by the working principle of the Fresnel lens, an ultrathin flat compound eye (UFCE) composed of an off-axis microlens array (OMLA) was developed. 3D lithography enabled the fabrication of the UFCE with a complex morphology. Compared to the traditional artificial compound eye (ACE), the thickness of the UFCE was greatly reduced. Meanwhile, a flat substrate and ultrathin structure allowed for direct integration of the UFCE into the surface of a CMOS. The resultant UFCE had a FOV of up to 110° and a resolution close to the diffraction limit and low dispersion. Furthermore, the UFCE allowed for fast imaging of mobile objects in any plane within the depth of field, which is the unique function of the UFCE. In brief, the fabricated UFCE based on OMLA reduces the complexity of constructing compound eye cameras while significantly optimizing the volume, suggesting an alternative method for creating high-performing optical elements with the possibility of simple integration and miniaturization.

Semi-Implantable Wireless Power Transfer (WPT) System Integrated With On-Chip Power Management Unit (PMU) for Neuromodulation Application

Miniaturization of the neuromodulation system is important for non-invasive or sub-invasive optogenetic application. This work presents an optimized wireless power transfer (WPT) system integrated with an on-chip rectification circuitry and an off-chip stimulation circuitry for optogenetic stimulation of freely moving rodents. The proposed WPT system is built using parallel transmitter (TX) coils on printed circuit board (PCB) and wire-wound based receiver (RX) coil followed by a seven-stage voltage doubler and a low dropout regulator (LDO) circuit designed in 180 nm standard Complementary Metal Oxide Semiconductor (CMOS) process. A pulse stimulation is used to stimulate the neurons which is generated using a commercially available off-the-shelf (COTS) components based oscillator circuit. The intensity of the stimulation is controlled by using a COTS based LED driver circuit which controls the current through the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> LED. The total dimension of the RX coil is 8 mm × 3.4 mm. The maximum power transfer efficiency (PTE) of the proposed WPT system is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 35% and the power conversion efficiency (PCE) of the rectifier is 52%. The proposed system with reconfigurable stimulation frequency is suitable for exciting different brain areas for long-term health monitoring.

Phase evolution in epitaxial Gd2O3 due to anneal temperature for silicon on insulator application

Epitaxial growth of Si on rare-earth oxides on Si wafer using sputter technology promises cheaper and high-volume manufacturing of Silicon-on-insulator (SOI) wafers over costly solutions like the smart-cut method. Further, rapid thermal annealing (RTA) in standard complementary metal–oxide–semiconductor (CMOS) processing affects the performance of SOI substrate through chemical and crystal phase change. Herein, we present a systematic study on the rich physical and chemical phase evolution of epitaxial Gd2O3 grown on Si (111) using RF sputtering subjected to RTA temperatures (850−1050 °C). First, X-ray diffraction analysis shows a significant enhancement of the epitaxial cubic phase in as-deposited Gd2O3 at an optimum RTA temperature of 850 °C, which is partially explained by epitaxial-regrowth of an amorphous layer at Gd2O3/Si interface as observed in Transmission Electron Microscopy. Secondly, the degradation of crystallinity beyond 900 °C is correlated with temperature-dependent Si diffusion into Gd2O3 that becomes observable by X-ray photoelectron spectroscopy. The Gd2O3 crystallinity is completely quenched into the amorphous gadolinium silicate phase at 1050 °C. Eventually, we employed X-ray reflectivity modeling to evaluate the film thickness variation with RTA. This study provides a detailed insight into the structural and chemical dynamics occurring in epitaxial-Gd2O3 film for CMOS-relevant temperatures.

Improving the Performance of Antenna-on-Chip by Effectively Illuminating the Artificial Magnetic Conductors Through Coupling Enhancement Structures

An antenna-on-chip (AoC) suffers from low radiation efficiency and gain because of the highly conductive silicon substrate used in standard complementary metal–oxide–semiconductor (CMOS) processes. Placing an artificial magnetic conductor (AMC) surface underneath the AoC not only isolates the antenna from the lossy substrate but also boosts its performance through in-phase reflection. Ideally, the AMC, which has a periodic structure, should be infinite in size, but practical chip sizes limit its dimensions. The gain of an AMC-backed AoC shows a positive correlation with the AMC lateral area. However, in the ultrathin stack-up of standard CMOS processes, the AMC cannot be irradiated uniformly by the antenna because of the physical illumination issue, so the AoC gain does not increase with the AMC area after the initial increase. To improve the illumination of the AMC by an AoC, this work introduces coupling enhancement structures (CES) that employ the available metal layers of the stack-up. The proposed AMC-backed AoC with CES demonstrates a gain of 9.8 dBi and radiation efficiency of 71% at 94 GHz, which are improvements of 4.3 dB in gain and 23% in radiation efficiency, respectively, compared to an AoC backed by a conventional AMC.

A Miniaturized CMOS-MEMS Amperometric Gas Sensor for Rapid Ethanol Detection

This study presents the design and implementation of a chip-scale amperometric ethanol sensor using the standard commercially available complementary metal oxide semiconductor (CMOS) process together with the post-CMOS micromachining processes. The presented amperometric sensor consists of a suspended plate with a microhole structure as the working electrode, a fully anchored plate with a microhole structure as the counter electrode, and a microcavity as the electrolyte reservoir. The metal and dielectric layers inherent in the standard CMOS process are exploited to realize these structures. The electrode with a microhole structure could enhance its surface area to improve the sensitivity of the sensor. The suspended working electrode covered a thinner Nafion <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\text {R}}$ </tex-math></inline-formula> layer could facilitate gas diffusion to shorten the response time of the sensor. To characterize the ethanol sensing, a Ni film is deposited on the working electrode. Measurements indicate the presented sensor has a sensing range of ppm (20–1000 ppm) at room temperature. Moreover, its sensitivity and response time are, respectively, 0.01 nA/ppm and 6 s. The presented design shows the CMOS-MEMS is a promising approach to realize the amperometric ethanol sensor.

A CNN-Based E-Nose Using Time Series Features for Food Freshness Classification

In this article, a convolutional neural network (CNN)-based electronic nose system is proposed, which utilizes time series features to classify the freshness of food. The electronic nose is composed of three elements: a highly sensitive miniaturized micro-electromechanical systems (MEMS) metal–oxide (MOX)–semiconductor gas sensor array, a complementary metal–oxide–semiconductor (CMOS) integrated circuit, and a CNN-based classification unit. The gas sensors exhibit exceptional sensitivity, low power consumption, and a small size. The interface circuit for sensor readout is fabricated using a standard 180-nm CMOS process, with an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\times1.5$ </tex-math></inline-formula> mm. The interface chip mainly consists of an analog-to-digital converter (ADC), an electrically erasable programmable read-only memory (EEPROM), an oscillator (OSC), power management, a heater driver, and a digital control circuit. Fixed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}{(}{t}{)}$ </tex-math></inline-formula> exposures are taken at specific intervals under gas input and output conditions. Time series features are extracted from a diverse set of sensor signals, which allows the subtle differences in various food odors at different freshness levels to be identified. The incorporation of time series feature extraction extends the data features, resulting in enhanced classification accuracy with a limited number of sensors. An abstract odor map input to the CNN is formed by combining the steady-state and transient information of the gas sensor response. The final freshness classification accuracy of 20 types of foods is 97.3%. The accuracy is improved by 6.5% after the implementation of time series feature extraction, demonstrating the significance of instantaneous fluctuation information for classification accuracy.

A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

Decreasing power consumption is the leading challenge for very-large-scale-integrated (VLSI) designers. This paper introduces an innovative prototype for a power-efficient standard or a fully-adiabatic binary-coded-decimal (BCD) 8421 to Excess-3 (XS-3) code converter. The proposed design is compared with traditional complementary metal oxide semiconductor (CMOS) as well as two popular fully adiabatic logic families: adiabatic dynamic CMOS logic (ADCL) and two phase clocked adiabatic static CMOS logic (2PASCL). This investigation was conducted at frequencies ranging from 100 to 900 MHz. The circuit employs 0.3 μm CMOS technology, with channel length and width set at 0.3 μm and 0.75 μm, respectively. The power savings for the proposed logic at 500 MHz when compared to standard CMOS logic, ADCL, and 2PASCL are 54.54%, 28.57%, and 16.67%, respectively.

Silicon Photonic Carrier-Assisted Differential Detection Receiver With High Electrical Spectral Efficiency for Short-Reach Interconnects

Coherent detection is advantageous in achieving high electrical spectral efficiency (ESE) relative to direct detection (DD), due to its capability of field recovery. However, the stringent requirement on the laser sources prevents it from being widely utilized in cost-sensitive short-reach applications. Carrier-assisted differential detection (CADD) was proposed to retrieve the optical field without needing for a narrow-linewidth local oscillator (LO) in a receiver. To realize a compact CADD receiver, silicon photonic (SiP) integration is therefore of particular interest since it leverages the standard complementary metal-oxide semiconductor (CMOS) compatible fabrication, offering high yield, low cost, and compact footprint. The fabrication process does not introduce III-V materials as the CADD receiver is LO-free. In this article, we fabricated a SiP integrated CADD receiver and demonstrated the transmission and reception of a 240-Gb/s orthogonal frequency division multiplexing (OFDM) 16-ary quadrature amplitude modulation (16-QAM) signal transmitted over an 80-km single-mode fiber (SMF) link, with a bit error ratio (BER) below the 25% overhead (OH) soft-decision forward error correction (SD-FEC) threshold. To the best of our knowledge, we achieve a record 5.2-b/s/Hz ESE per polarization for an integrated DD receiver.

On-chip micro-ring resonator array spectrum detection system based on convex optimization algorithm.

We propose an all on-chip micro-ring resonator array spectrum detection system (MRRAS). Micro-ring resonator array as the core is used to construct the transmission matrix of the system. The theoretical analysis of the spectrum detection system is completed with waveguide transmission theory and spectrum construction method based on convex optimization algorithm. In the experiment, we obtain the priori information of the transmission matrix of the system, then detect the output intensity of unknown spectrum through MRRAS, and construct the under-determined matrix equations when the number of micro-rings is much smaller than that of reconstructed wavelengths. Convex optimization algorithm is employed to obtain the least normsolution of the under-determined matrix equations, which enables fast spectrum reconstruction. The experimental results show that the spectrum detection system is constructed using three micro-ring resonators with 4μm radius, enabling the compact footprint. In addition, the silicon nitride based photonic platform is fully compatible with standard complementary metal oxide semiconductor (CMOS) processes. The system operating bandwidth is more than 12nm and the resolution is better than 0.17nm.