Formal Verification of Sequential Circuits in Superconducting Single Flux Quantum Technologies

Abstract

Logical equivalence checking is one of the most effective verification steps in the entire design process of integrated circuits. However, it faces challenges in emerging technologies due to differences between its logic models and those of the standard complementary metal oxide semiconductor (CMOS). This paper presents qSC, an equivalence checking framework targeting <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sequential</i> circuits mapped to rapid superconducting single-flux-quantum (RSFQ) logic circuits. In addition to a logical checking module, qSC also includes several structural checking modules. The structural checking modules are used to check whether the circuit meets the design rules of superconducting RSFQ logic circuits. The main difficulty of verifying nonlinear <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sequential</i> circuits is in finding the levels of logic cells in the circuit for full-path-balancing checking for which the conventional topological sorting algorithm of acyclic digraphs is not applicable. The key is to define and calculate levels for nodes in a cyclic graph and to avoid any loop trap. Hence, a new algorithm is presented for full-path-balancing checking of the cyclic digraph that satisfies all of these desirable features. The experimental results show the feasibility of qSC on sequential circuits implemented in RSFQ technologies.