Standard 6T SRAM Research Articles

A 45nm AND 65nm CMOS IMPLEMENTATION OF 12T SRAM CELL WITH SOFT ERROR READ STABILITY OF MULTINODE UPSET RECOVERABILITY FOR AEROSPACE APPLICATION

With technology advancing rapidly, the size of transistors and the distance between them is decreasing quickly. This reduction in size is causing the critical charge of sensitive nodes in SRAM cells to decrease, making them more susceptible to soft errors, especially in aerospace applications. When a radiation particle strikes a open node in a standard 6T SRAM cell, the storage data in the cell can be changed, leading to a single-event upset (SEU). To address this issue, a new Soft Error Read and write Stability improves Low Power 12T (SARP12T) SRAM cell has been introduced in this study to reduce the impact of SEUs. The performance of SARP12T has been compared to other recently developed soft-error-aware SRAM cells like QUCCE12T, QUATRO12T, RHD12T, RHPD12T, and RSP14T. SARP12T is designed for the recoverability of all stored data in sensitive nodes even if they are affected by radiation strikes. Additionally, SARP12T can overcome single-event multi-node upsets (SEMNUs) that may happened at its sensitive node pair. This proposed cell also boasts the higher read stability, as the storage node holding '0' can regain from any upset during read operations. Moreover, SARP12T consumes the minimum amount of hold power, has greater write ability, and lower write delay compared to other similar cells. Despite a almost greater read delay and higher read and write energy consumption, the improvements in the proposed SARP12T cell make it a promising solution for mitigating soft errors in SRAM cells

A robust radiation resistant SRAM cell for space and military applications

Many charged particles in space, including α-particles, neutrons, heavy ions, electrons, and photons, wreak havoc on the stability and reliability of memory circuits. In addition, these high-energy particles produce an ion track within the memory chip, which disrupts the storage bit. Standard 6T SRAM cannot withstand this upset condition. This paper presents a novel RRS-14T radiation-resistant SRAM memory cell with redundant nodes and a polar design to address the soft error issue. The performance of the proposed RRS-14T memory cell is compared to the performance of existing radiation-resistant memory cells, such as RHS-14T, RHMC-12T, NRHC-14T, QCCS-12T, HRRT-13T, and RHBD-13T. The RRS-14T cell protects against single and multiple-node disruptions. The read stability of the proposed RRS-14T memory cell is 2.83x/ 1.5x/ 2.10x/ 1.34x/ 3.38x/ 1.68x greater than the existing RHS-14T/ RHMC-12T/ NRHC-14T/ QCCS-12T/ HRRT-13T/ RHBD-13T memory cells. Moreover, 1.08x/ 1.27x/ 1.06x/ 1.05x/ 1.16x/ 1.07x larger write trip voltage than RHS-14T/ RHMC-12T/ NRHC-14T/ QCCS-12T/ HRRT-13T/ RHBD-13T memory cells. In addition, the write access time, hold power, and critical charge are enhanced when the supply voltage is at 1 V.

An efficient radiation hardening SRAM cell to mitigate single and double node upset soft errors

Various charged particles in space, including α- particles, neutrons, heavy ions, and photons, create stability and reliability concerns in memory circuits. Furthermore, these particles generate an ion track within the memory device, which disrupts the storage bit. The standard 6T SRAM is very susceptible to this upset. To address this issue, several authors proposed radiation-hardened SRAM cells. Most of the works consider adding redundant nodes to the memory cell. This study shows a new RHBD-14T SRAM memory cell with redundant nodes to deal with the soft error problem. The proposed RHBD-14T memory cell performance is compared to that of recent reliable radiation-hardened memory cells such as SEA-14T, QCCS-12T, NRHC-14T, RHMC-12T, HPHS-12T, SIMR-18T, SERSC-16T, RHWC-12T. The proposed RHBD-14T cell protects against single and double-node disruptions by considering minimum sensitive nodes layout area separation concept. Furthermore, proposed RHBD-14T exhibits 1.45x/ 1.06x/ 1.54x/ 1.25x/ 2.86x/ 1.39x/ 1.31x/ 1.57x times greater read stability than existing SEA-14T/ QCCS-12T/ NRHC-14T/ RHMC-12T/ HPHS-12T/ SIMR-18T/ SERSC-16T/ RHWC-12T memory cells.

A soft error upset hardened 12T-SRAM cell for space and terrestrial applications

Various charged particles in space, including alpha particles, neutrons, heavy ions, and photons, pose reliability and stability concerns for memory circuits. These particles also create an ion track in the memory chip, disrupting the storage bit. The standard 6T SRAM is particularly susceptible to these disturbances. Several researchers suggest employing radiation-hardened SRAM cells to solve this problem. Most studies examine the inclusion of redundant nodes in the memory cell to recover the lost bit. This paper shows a new SEUH-12T SRAM memory cell with redundant nodes to deal with the soft error problem. The proposed SEUH-12T memory cell performance is compared to that of reliable radiation-hardened memory cells such as Quatro-10T, We-Quatro-12T, QCCS-12T, STS-10T, RHMC-12T, and RHWC-12T. The proposed SEUH-12T cell protects against single and multiple node disruptions by considering minimum sensitive nodes layout area separation concept. Furthermore, proposed SEUH-12T exhibits 8.5×/ 6.3×/ 5.6×/ 1.4×/ 1.2×/ 1.4×/ 1.04× times greater read stability than existing 6T-SRAM/ Quatro-10T/ We-Quatro-12T/ QCCS-12T/ STS-10T/ RHMC-12T/ RHWC-12T memory cells.

Soft Error Simulation of Near-Threshold SRAM Design for Nanosatellite Applications

This paper presents the benefit of the near-threshold design of random-access memory (SRAM) design to reduce software errors during very low-power operations in nanosatellites. The near-threshold design is based on an optimization of the use of the Schmitt trigger structure for a 45 nm technology. The results of the soft error susceptibility of the optimized design are compared to a standard 6T SRAM cell. These two designs are modeled and validated by comparing the results with experimental measurements of both static noise margin (SNM) and single event upset (SEU). The optimized circuit reduces the multiple upsets occurrence from 95% down to 14%. Based on the use of simulation tools, the paper demonstrates that the near-threshold design of SRAM is an excellent candidate for the radiation point of view for agile nanosatellites. The results computed for the near-threshold SRAM device demonstrate an improvement of a factor of up to 25 of the soft error rate (SER) in a GEO orbit.

CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration

SRAM-based computing-in-memory (CIM) has been widely explored to accelerate neural networks (NNs). However, it is challenging to store all weights of many modern NNs due to limited on-chip SRAM capacity. This bottleneck induces a large amount of off-chip DRAM accesses and impedes the improvement of performance and energy efficiency. This paper proposes a new approach of computing in resistive random-access memory (ReRAM)-assisted energy-and area-efficient SRAM (CREAM) for accelerating large-scale NNs while eliminating the DRAM access. The NN weights are all stored in high-density on-chip ReRAMs and restored to the proposed non-volatile SRAM (nvSRAM) CIM cells with array-level parallelism. Furthermore, to deal with the influence of ReRAM and CMOS variations, a novel layer-wise and bit-wise weight-configuration search algorithm is proposed by leveraging different sensitivity of each layer in NN models. A data-aware weight-mapping method is also presented to efficiently map NN models to ReRAMs in CREAM for high computation parallelism. The experiment results show 10.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> weight storage density over the standard 6T SRAM array. Evaluations of ResNet-18 and VGG-9 on CIFAR-10/CIFAR-100 datasets show up to 3.47 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> and 1.70 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> energy efficiency over two baseline designs of SRAM-CIM and ReRAM-CIM, respectively, in addition to 15.6% higher accuracy than ReRAM-CIM under device variations.

A Novel Low-Power and Soft Error Recovery 10T SRAM Cell.

In SRAM cells, as the size of transistors and the distance between transistors decrease rapidly, the critical charge of the sensitive node decreases, making SRAM cells more susceptible to soft errors. If radiation particles hit the sensitive nodes of a standard 6T SRAM cell, the data stored in the cell are flipped, resulting in a single event upset. Therefore, this paper proposes a low-power SRAM cell, called PP10T, for soft error recovery. To verify the performance of PP10T, the proposed cell is simulated by the 22 nm FDSOI process, and compared with the standard 6T cell and several 10T SRAM cells, such as Quatro-10T, PS10T, NS10T, and RHBD10T. The simulation results show that all of the sensitive nodes of PP10T can recover their data, even when S0 and S1 nodes flip at the same time. PP10T is also immune to read interference, because the change of the '0' storage node, directly accessed by the bit line during the read operation, does not affect other nodes. In addition, PP10T consumes very low-holding power due to the smaller leakage current of the circuit.

High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications

Static random access memory (SRAM) plays a key role in the overall performance of electronic systems because of its rapid data processing and transmission speed; however, when the system power supply is cut off, the data stored in the nodes are lost. Thus, this article proposes four nonvolatile SRAM (NVSRAM) cells that use unilateral or bilateral structures with dual complementary series resistive random access memory (RRAM) devices. It is found that the read, write, and hold static noise margins (HSNMs) are comparable with those of the standard 6T-SRAM. Moreover, the store and restore operations operate in parallel at high speed. The store operation delay is only 6 ns for unilateral structures and 5 ns for bilateral structures, and the restore delay is only 10 ns for unilateral structures and 6 ns for bilateral structures. The maximum power consumption among the four structures for storing and restoring a “1” are 1.545 pJ/bit and 134.5 fJ/bit, respectively. Furthermore, the dual complementary series resistor structures can achieve a high restore yield at a resistance ratio of 1.5. Therefore, a high restore yield can be achieved even with large resistance fluctuations caused by the voltage, time, and process.

SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks

This paper presents a mixed-signal SRAM-based in-memory computing (IMC) macro for processing binarized neural networks. The IMC macro consists of <inline-formula> <tex-math notation="LaTeX">$128\times 128$ </tex-math></inline-formula> (16K) SRAM-based bitcells. Each bitcell consists of a standard 6T SRAM bitcell, an XNOR-based binary multiplier, and a pseudo-differential voltage-mode driver (i.e., an accumulator unit). Multiply-and-accumulate (MAC) operations between 64 pairs of inputs and weights (stored in the first 64 SRAM bitcells) are performed in 128 rows of the macro, all in parallel. A weight-stationary architecture, which minimizes off-chip memory accesses, effectively reduces energy-hungry data communications. A row-by-row analog-to-digital converter (ADC) based on 32 replica bitcells and a sense amplifier reduces the ADC area overhead and compensates for nonlinearity and variation. The ADC converts the MAC result from each row to an N-bit digital output taking 2^N-1 cycles per conversion by sweeping the reference level of 32 replica bitcells. The remaining 32 replica bitcells in the row are utilized for offset calibration. In addition, this paper presents a pseudo-differential voltage-mode accumulator to address issues in the current-mode or single-ended voltage-mode accumulator. A test chip including a 16Kbit SRAM IMC bitcell array is fabricated using a 65nm CMOS technology. The measured energy- and area-efficiency is 741-87TOPS/W with 1-5bit ADC at 0.5V supply and 3.97TOPS/mm², respectively.

A highly reliable radiation tolerant 13T SRAM cell for deep space applications

This paper proposes a highly reliable radiation-tolerant 13T (HRRT 13T) SRAM cell for deep-space applications. The proposed SRAM cell design can effectively tolerate radiation events. The design metrics of the proposed SRAM cell are compared with conventionally used SRAM cells like QUCCE 10T, QUCCE 12T and standard 6T SRAM cells. The proposed SRAM cell consumes 9.4% and 14% lesser hold power (HPWR) compared to QUCCE 10T and QUCCE 12T SRAM cells, respectively. The proposed SRAM cell exhibits 12.7%, 3.63% and 11.7% shorter read access time (TRA) compared to QUCCE 10T, QUCCE 12T and 6T SRAM cells, respectively at a nominal supply voltage (VDD) of 0.7 V. The proposed HRRT 13T SRAM cell exhibits higher read stability compared to other conventionally used SRAM cells. This has been validated by 2.92×, 2.33× and 2.06× higher read static noise margin (RSNM) exhibited by the proposed cell compared to the 6T, QUCCE 10T and QUCCE 12T SRAM cells, respectively at VDD = 0.7 V. The proposed SRAM cell exhibits high radiation tolerance capability compared to the conventionally used SRAM cells. This has been proved by 94.1%, 17.8% and 10.0% higher critical charge (QC) of the proposed cell compared to 6T, QUCCE 10T and QUCCE 12T SRAM cells, respectively at VDD = 0.7 V. The proposed cell achieves all these improvements at the expense of 1.05×, 1.38× and 1.36× longer write delay (TWA) compared to QUCCE 10T, QUCCE 12T and 6T SRAM cells, respectively at VDD = 0.7 V. Extensive simulations on SPICE using 16-nm CMOS technology are performed to validate the theoretical design of the proposed SRAM cell.

Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T SRAM With Multi-Node Upset Recoverability for Aerospace Applications

With the advancement of technology, the size of transistors and the distance between them are reducing rapidly. Therefore, the critical charge of sensitive nodes is reducing, making SRAM cells, used for aerospace applications, more vulnerable to soft-error. If a radiation particle strikes a sensitive node of the standard 6T SRAM cell, the stored data in the cell are flipped, causing a single-event upset (SEU). Therefore, in this paper, a Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T (SARP12T) SRAM cell is proposed to mitigate SEUs. To analyze the relative performance of SARP12T, it is compared with other recently published soft-error-aware SRAM cells, QUCCE12T, QUATRO12T, RHD12T, RHPD12T and RSP14T. All the sensitive nodes of SARP12T can regain their data even if the node values are flipped due to a radiation strike. Furthermore, SARP12T can recover from the effect of single-event multi-node upsets (SEMNUs) induced at its storage node-pair. Along with these advantages, the proposed cell exhibits the highest read stability, as the &#x2018;0&#x2019;-storing storage node, which is directly accessed by the bitline during read operation, can recover from any upset. Furthermore, SARP12T consumes the least hold power. SARP12T also exhibits higher write ability and shorter write delay than most of the comparison cells. All these improvements in the proposed cell are obtained by exhibiting only a slightly longer read delay and consuming slightly higher read and write energy.

A Novel Loadless 6T-SRAM Cell with Isolated Read Port

Conventional 6T SRAM cell parameters have degraded with scaling to newer technologies and reduced power supply voltages. This has led to numerous tradeoffs with respect to cell stability, performance, power, and area. In this paper, a novel Dual Port SRAM design has been introduced that aims at improving the read and write ability of the standard 6T SRAM cell. The simulations for the proposed structure have been performed on HSpice using PTM 32nm Technology node. The comparison of results with the standard cell showed an increase of 84.76% in read margins and 40.81% in the write stability. Also, the proposed design was found to be capable of writing at high frequencies as the minimum pulse width of WWL for a successful write operation was determined to be 25ps. Further, the design also improves in the areas of WTV, SVNM, WTP, SPNM

WITHDRAWN: Low power performance SRAM cell design

The Static Random Access Memory (SRAM) is shown vital in high performance portable VLSI Chips due to their performance and storage density. This paper presents the evaluating point by point recreation derive for the memory cells inform of the power, speed, and area investment funds acquired in the advanced cell configuration when contrasted with the standard regular architecture. The adiabatic low power technique is implements to enrich the configuration of 6T-SRAM cell. The approach and application of this adiabatic driver the more loss of energy dissipation to the ground (0 V) with ‘1’ to‘0’ transition is decreased to a larger degree in the memory cell. This method gives a lower degree of power reduction results compared with the standard adiabatic 6T-SRAM cell.

Design of 10T SRAM cell with improved read performance and expanded write margin

The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters turns out to be most relevant issues in the nanometre SRAM design. The authors propose a 10T SRAM circuit that shows reduction in read power dissipation while maintaining fair performance and stability. Impression of process parameter variations on various design metrics such as read power, read current and data retention voltage of the proposed cell are presented and compared with already proposed SRAM cell. The projected topology offers differential read and single-ended write operation. The read margin and write margin are enhanced by 8.69% and 16.85% respectively in comparison to standard 6T SRAM cell even when single-ended write operation is performed. Furthermore, the read and write delay of projected topology improve by 1.78× and 2.326× in comparison with conventional 6T bit SRAM cell. In FF process corner, the proposed topology shows lowest data retention voltage (DRV) and minimum variation in DRV with temperature. Out of all considered topologies, the proposed circuit is optimized to minimum power delay product during read operation. Further, standby power and read power of proposed 10T cell is reduced by 34.65% and 2.03× in contrast to conventional 6T SRAM at 0.9 V supply voltage. Analysis of process variations tolerance read power and read current is also presented with 45 nm generic process design kit technology file using cadence virtuoso tool.

2D Strain FET (2D-SFET)-Based SRAMs—Part II: Back Voltage-Enabled Designs

In Part I of this article, we had discussed the device characteristics of 2D Strain FET (2D-SFET) and 6T-SRAM with 2D-SFET used as a drop-in replacement for 2D-FET. Here (in Part II), we propose 2D-SFET-based 6T-SRAM designs targeted toward improving cell robustness (which is otherwise low in 2D-SFET SRAMs analyzed in Part I). Our 2D-SFET-based 6T-SRAM designs, namely Schmitt Trigger (ST) SRAM, Schmitt Trigger with Data-Driven Access Feedback (ST-DAF) SRAM and Schmitt Trigger with Dual Word-line (ST-DWL) SRAM leverage back voltage ( ${V}_{B}$ )-driven dynamic bandgap change in 2D-SFET to mitigate the design conflicts. We show that in all designs ST action is achieved by dynamically tuning the strength of pull-up 2D-SFETs enabled by ${V}_{B}$ . This along with other optimizations result in up to 33% higher read stability in the proposed designs over 2D-FET-based standard 6T SRAM, while mitigating the design conflicts present in standard 6T SRAMs. Our analysis also highlights the benefits and trade-offs for write and hold operations for each of our designs. All the proposed 2D-SFET ${V}_{B}$ -enabled SRAMs achieve the enhanced functionalities at iso -area compared to 2D-SFET drop-in SRAM in Part I.

A Low-Voltage-Driven High-Voltage SRAM Pixel Circuit for Power Reduction in a Digital Micro-Display Panel

A new SRAM-based pixel circuit is presented for use in a high-voltage digitally-driven pixel array in a micro-display panel. The pixel circuit is based on the standard 6T SRAM structure, but uses two more transistors of which gate dc-bias is controlled to adjust the pull-up strength of the inverters in the SRAM. This allows the pixel circuit to be operated with low-voltage row- and column-line signals while holding the stored logic in a high-voltage level. As a result, power and area of the pixel driving circuits are greatly reduced. The added two transistors do not necessitate area overhead if the pixels are to be individually separated with rectangular shape, which is true in many cases. To verify proper operation and power reduction efficacy of the proposed SRAM pixel circuit, a simple $100\times 200$ digital pixel array, together with row- and column-line drivers, is implemented using a 0.13-$\mu \text{m}$ CMOS technology and 1.5-V/3.3-V supplies. The measurement results show that, with the optimum bias for the two added transistors, total power dissipation including pixel array and driver power can be reduced by about as much as 78 %, which is very close to the theoretical limit of 79 % (= (1.5/3.3) 2 ).

A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET

This paper proposes a new 8T nonvolatile SRAM (nvSRAM) cell employing ULP FinFETs and ferroelectric FinFETs to enable energy-efficient and low-latency store/recall operations. Different from other types of nvSRAM requiring additional circuitry or nonvolatile memories connected to a standard 6T SRAM cell to achieve nonvolatility, the proposed hybrid nvSRAM cell reduces the area penalty by embedding the nonvolatile ferroelectric FinFETs in a 6T SRAM cell without sacrificing the cell stability, read/write performance and power consumption.

Characterization of single-ended 9T SRAM cell

We present a circuit-level technique of designing a lower write-power along with variability-resistant 9-MOFTET static random-access memory cell. Our proposed bitcell exhibits lower write-power consumption owing to reduction of activity factor and breakup of feedback path between the cross-coupled inverters during write operation. It exhibits higher read static noise margin (by 3.09 ×) compared with standard 6T SRAM cell @ minimum-area. LP9T shows higher static margin for write operation (by 41%) compared with 8T (S6T) @ iso-area (minimum-area). These improvements are achieved due to breakup of feedback path during the process of writing a bit on to the storage node. The paper investigates in detail the influence of variation in process related parameters, environmental parameters such as supply voltage and temperature on most of the important design parameters of the bitcell and compares the obtained simulation results with conventional 6-MOSFET (6T) and 8-MOSFET (8T) bitcells. It demonstrates its invariableness by showing 1.5 × tighter disperse in read time variability with a cost of 1.41 × higher read time compared with S6T @ minimum-area. It also exhibits 39% narrower disperse in read time variability in comparison to 8T @ iso-area. It draws lower power (2.06 ×) from supply voltage while flipping of stored data during write mode compared with standard 8T SRAM cell @ iso-area. It also compares key design metrics of LP9T with those of few other 9T SRAM cells found in the literature. This work also realizes the proposed design using CNFET. The CNFET-based design outperforms its CMOS counterpart in all respect.

Design of memristor based low power and highly reliable ReRAM cell

A CNFET-based nonvolatile 4CNFET2M resistive RAM (ReRAM) cell is proposed in this paper. In this design, four CNFETs are employed as high-speed, low power and high endurance switches while the two memristors constitute the memory element. In this paper, the proposed 4CNFET2M ReRAM has been compared with the standard 6T SRAM (S6T) cell and the contemporary 2T2M ReRAM cell. The proposed cell shows 1.68 ×/2.14 × shorter read delay (TRA) when compared to S6T/2T2M while exhibiting 4.16 × shorter write delay (TWA) than that of 2T2M @ VDD = 1 V. Moreover, at VDD = 1 V, it displays a 2.32 × narrower spread in TWA than 2T2M as well as 8.0 ×/7.25 × narrower spread in TRA than that of S6T/2T2M. The proposed cell consumes 2.57 × 106 ×/2.70 × lower hold power (HPWR) than that of S6T/2T2M at VDD = 1 V. In addition, it exhibits tolerance to variations in temperature as well as pitch and Vth of memristor. All this is achieved at a 32.44 × penalty in TWA when compared to S6T. The use of CNFET devices, which possess far superior electrical characteristics in comparison to traditional CMOS devices, integrated with memristor technology, paves the way for such major improvements in design metrics of the proposed cell.

Stability analysis of Sub-threshold 6T SRAM cell at 45 nm for IoT application

In ultra-Low power application the supply volt- age in the circuit is as minimum as possible to correct perform the operation. Reducing the supply voltage below the threshold Voltage of transistor is known as sub threshold voltage that affects the delay as well as stability parameter of the Circuit. In this paper body biased technique is applied at standard 6T SRAM which improve the static Current Noise Margin(SINM) and Write trip Current by the factor of 4.15 times and 4.7 times respectively from the Conventional (conv) 6T SRAM. SINM defined the read stability whereas WTI are write ability Parameters of the circuit. In the Sub threshold region delay parameter of the circuit increased, but in this paper delay and power of the proposed circuit are going to be degrades 2.34 times and 4.39 times from the conv. 6T SRAM at different Process Corner i.e. the Performance of the device get increased. In this paper conventional (Conv.)6T and Proposed(PP) 6T both have same W/L ratio at supply voltage of 400mv.