A Novel Loadless 6T-SRAM Cell with Isolated Read Port

Abstract

Conventional 6T SRAM cell parameters have degraded with scaling to newer technologies and reduced power supply voltages. This has led to numerous tradeoffs with respect to cell stability, performance, power, and area. In this paper, a novel Dual Port SRAM design has been introduced that aims at improving the read and write ability of the standard 6T SRAM cell. The simulations for the proposed structure have been performed on HSpice using PTM 32nm Technology node. The comparison of results with the standard cell showed an increase of 84.76% in read margins and 40.81% in the write stability. Also, the proposed design was found to be capable of writing at high frequencies as the minimum pulse width of WWL for a successful write operation was determined to be 25ps. Further, the design also improves in the areas of WTV, SVNM, WTP, SPNM