Stacked Circuit Research Articles

DC-biased Suzuki stack circuit for Josephson-CMOS memory applications

Josephson-CMOS hybrid memory leverages the high speed and low power operation of single-flux quantum logic and the high integration densities of CMOS technology. One of the commonly used type of interface circuits in Josephson-CMOS memory is a Suzuki stack, which is a latching high-voltage driver circuit. Suzuki stack circuits are typically powered by an AC bias voltage that has several limitations such as synchronization and coupling effects. To address these issues, a novel DC-biased Suzuki stack circuit is proposed in this paper. As compared to a conventional AC-biased Suzuki stack circuit, the proposed DC-biased design can provide similar output voltage levels and parameter margins, approximately two times higher operating frequency, and three orders of magnitude lower heat load of bias cables.

A high speed and power efficient multiplier based on counter-based stacking

<span>High speed and competent addition of various operands is an essential operation in the design any computational unit. The swiftness and power competence of multiplier circuits plays vital role in enlightening the overall performance of microprocessors. Multipliers play crucial role in the design of <a name="_Hlk140074299"></a>arithmetic logic unit (ALU) or any digital signal processor (DSP) that are effectively employed for filtering and convolution operations. The process of multiplication either binary numbers or fixed-point numbers yields in enormous partial products that are to be added to get final product. These partial products in number and the process of summing up partial products dictate the latency and power consumption of the multiplier design. Here, we present a novel binary counter design that hires stacking circuits, that groups all logic “1” bits as one, followed by a novel symmetric method to merge pairs of 3-bit stacks into 6-bit stacks and then changes them to binary counts. This results in drastic improvements in power and area utilization of the multiplier. Additionally, this paper also focuses on implementation of novel approximate compressor and exploits the same for the design of approximate multipliers that can be effectively employed in any electronic systems that are characterized by power and speed constraints.</span>

Virtual Inertia Response and Frequency Control Ancillary Services From Hydrogen Electrolyzers

This paper presents the modeling foundations to study the capabilities of hydrogen electrolyzers (HEs) to provide frequency control ancillary services (FCAS), including virtual inertia and primary and secondary frequency response. To do so, we propose a general, unified HE dynamic model for the electrolyzer stack circuit, power-electronics interface (PEI), and relevant converter-level control loops. The equivalent circuit of the stack is derived from its current transfer function, with poles and zero obtained from its step response characteristics (e.g., rise/settling time). The stack model also considers relevant physical nonlinearities and downstream hydrogen buffer/process operational constraints. The PEI control loops account for stack model parameters, hydrogen production operational constraints, stack temperature dynamics, and active power reference generation strategy for contingency and regulation frequency support services. Further, we propose a virtual synchronous machine (VSM) control approach to study the VSM HE capabilities to also provide virtual inertia response. We apply the modeling to both alkaline and proton exchange membrane (PEM) technologies, including design of appropriate control schemes. Finally, we assess the FCAS performance of alkaline and PEM HEs via dynamic simulation of the Australian south-east interconnection in a 50%-renewable scenario, also discussing comparison and cooperation with battery energy storage systems.

Suzuki Stack Circuit With Differential Output

Suzuki stack circuits, a type of latching high-voltage driver circuit, are widely used in Josephson–CMOS hybrid memories. The existing Suzuki stack designs utilize only single-ended signaling when connected to a CMOS amplifier. In this article, a Suzuki stack circuit with a differential output is proposed by producing both the positive and negative output voltages. The negative output voltage is produced by using a negative biasing network and a negative single-flux quantum (SFQ) input pulse, which is generated by the proposed positive-to-negative SFQ converter. As compared to a conventional single-ended Suzuki stack circuit, the proposed differential design can provide two times higher output voltage swing and better immunity to noise without degrading the operating margins. Potential advantages and drawbacks of the proposed circuit are explored in this article.

Optimization of Suzuki Stack Circuit to Reduce Power Dissipation

Superconductor–semiconductor hybrid circuits can combine the benefits of the high-speed and low-power operation of single-flux quantum circuits and high integration densities of CMOS technology such as memory. The Suzuki stack, a type of Josephson latching driver/amplifier, is a widely used interface circuit in Josephson–CMOS hybrid memories. Due to the limited cooling power at cryogenic temperatures, the power dissipation is becoming an important concern, especially in large-scale systems. An optimization technique to significantly reduce the power dissipation of Suzuki stack circuits is proposed in this article. The proposed design can reduce the power dissipation by 30–70% while causing a voltage drop of 2–9% in the output voltage depending on the circuit parameter configuration. The tradeoffs between the power dissipation and output voltage characteristics are discussed. The proposed design can operate correctly within at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\pm$</tex-math></inline-formula> 20% of process parameter variations as demonstrated with extensive simulations.

Yttrium Oxyfluoride Coatings Deposited by Suspension Plasma Spraying Using Coaxial Feeding

The recently discovered yttrium oxyfluoride (YOF) coating has been found to be a highly promising plasma-resistant material which can be coated onto the inner wall of the dry etching chambers used in the manufacturing of the three-dimensional stacking circuits of semiconductors, such as vertical NAND flash memory. Here, the coating behavior of the YOF coating which was deposited by suspension plasma spraying was investigated using a high-output coaxial feeding method. Both the deposition rate and density of YOF coatings increased with the plasma power, which was determined by the gas ratio of Ar/H2/N2 and the arc current. The coating thicknesses were 58 ± 3.4, 25.8 ± 2.1, 5.6 ± 0.6, and 0.93 ± 0.4 µm at plasma powers of 112, 83, 67, and 59 kW, respectively, for 20 scans with a feeding rate of the suspension at 0.045 standard liters per minute (slm). The porosities were 0.15% ± 0.01%, 0.25% ± 0.01%, and 5.50% ± 0.40% at corresponding plasma powers of 112, 83, and 67 kW. High-resolution X-ray diffraction (HRXRD) shows that the major and minor peaks of the coatings which were deposited at 112 kW stem from trigonal YOF and cubic Y2O3, respectively. Increasing the flow rate of the atomizing gas from 15 slm to 30 slm decreased the porosity of the YOF coating from 0.22% ± 0.03% to 0.07% ± 0.03%. The Vickers hardness of the YOF coating containing some Y2O3 deposited at 112 kW was 550 ± 70 HV.

3D-FOWLP에서 TMV (Through Mold Via) 유형(Cu-Via, EMC Filling Via)에 따른 열기계적 특성 시뮬레이션 분석

Currently, Through mold via (TMV) technology is being actively researched for 3D-Intergrated Circuit stacking in fan-out wafer level packaging (FOWLP). However, because of problems, such as extrusion, cracking, and warping of the Cu materials forming the via, its mass production process is difficult. Moreover, sudden temperature changes when using the chips cause heat fatigue in the TMV. To overcome this problem, the Epoxy molding compound (EMC) filling via (EFV) is being developed to form a thin Cu via through a deposition process and then fill the interior of the via with EMC. Through simulations, this study analyzed the thermal-mechanical properties of the TMV in the 3D-FOWLP according to the type of TMV (Cu via and EFV) to minimize the thermal stress and deformation generated when using the chip. Consequently, EFV exhibits better thermal-mechanical properties in comparison with those of the Cu via when the 3D-FOWLP is deformed by heat.

Design and Analysis of a Low Power Binary Counter-based Approximate Multiplier Architecture

Multiplication has become the fundamental arithmetic operation in modern electronic world. Many researches in Signal processing and image processing applications are looking for energy efficient architectures. These applications exhibit error tolerance thus laying foundation for approximation techniques. The proposed work utilizes a new binary counter for partial product accumulation in a segmentation based approximate multiplication technique. The fundamental building block of the counter is a 3-bit stack circuit, which combines each of “Logic 1” bits collectively, after which a stacking process is done to convert two 3-bit modules into a 6-bit stack module. The counter circuit is obtained by converting the bit stacks to binary counts, without any XOR gates on the critical line of operation. This leads to design of binary counters with effective yield of power and delay. Moreover, applying these counters for partial product accumulation in the approximate multipliers found to be more effective when compared with conventional techniques. In future, these counter based approximate multipliers can be utilized to design energy efficient filters for image processing and signal processing applications.

Symmetric stacked fast binary counters based on reversible logic

A Symmetric Stacked Fast Binary counter design is proposed in this paper. In the circuit design, the first phase is occupied by 3-bit stacking circuits, which are further followed by combining circuits. The resultant novel circuit thus becomes a 6-bit stacker. A 6:3 counter has been chosen as an example to demonstrate the working of the proposed circuit. The proposed circuit is further implemented by using reversible logic gates. Heat dissipation is a major problem in the designing of a digital circuit. Rolf Landauer has proved that the information loss in a digital circuit is directly proportional to the energy dissipation. The proposed modified Symmetric Stacking counter is implemented using reversible logic gates thus reducing the power dissipation of the circuit.

Precision 3D profile in-line measurement of through-silicon via (TSV) based on high-frequency spectrum signals in the pupil plane

As a deep and fine vertical via, through-silicon via (TSV) is a key factor in three-dimensional (3D) integrated circuit stack, which can pass through a silicon wafer or chip for 3D integration. TSV’s 3D profile metrology is one of the key issues in process control. In this work, we propose and demonstrate a non-destructive in situ measurement technology that can be used to measure the 3D geometric profiles of TSV with an aspect ratio of 10. The optical system designed by us can collect high-frequency signals, which contain the whole geometry information of the TSV in the pupil plane. This measurement is proven effective by analysing the high-frequency spectrum of the pupil plane. Our 3D measurement technology can measure TSV profile diameters as small as 5 μm with an aspect ratio of 10:1. The measurement accuracy is ±0.5% comparable with that of SEM measurements using the same sample.

Interface charge trapping induced flatband voltage shift during plasma-enhanced atomic layer deposition in through silicon via

A Through Silicon Via (TSV) is a key component for 3D integrated circuit stacking technology, and the diameter of a TSV keeps scaling down to reduce the footprint in silicon. The TSV aspect ratio, defined as the TSV depth/diameter, tends to increase consequently. Starting from the aspect ratio of 10, to improve the TSV sidewall coverage and reduce the process thermal budget, the TSV dielectric liner deposition process has evolved from sub-atmospheric chemical vapour deposition to plasma-enhanced atomic layer deposition (PE-ALD). However, with this change, a strong negative shift in the flatband voltage is observed in the capacitance-voltage characteristic of the vertical metal-oxide-semiconductor (MOS) parasitic capacitor formed between the TSV copper metal and the p-Si substrate. And, no shift is present in planar MOS capacitors manufactured with the same PE-ALD oxide. By comparing the integration process of these two MOS capacitor structures, and by using Elastic Recoil Detection to study the elemental composition of our films, it is found that the origin of the negative flatband voltage shift is the positive charge trapping at the Si/SiO2 interface, due to the positive PE-ALD reactants confined to the narrow cavity of high aspect ratio TSVs. This interface charge trapping effect can be effectively mitigated by high temperature annealing. However, this is limited in the real process due to the high thermal budget. Further investigation on liner oxide process optimization is needed.

Fast Binary Counters Based on Symmetric Stacking

In this brief, a new binary counter design is proposed. It uses 3-bit stacking circuits, which group all of the “1” bits together, followed by a novel symmetric method to combine pairs of 3-bit stacks into 6-bit stacks. The bit stacks are then converted to binary counts, producing 6:3 counter circuits with no xor gates on the critical path. This avoidance of xor gates results in faster designs with efficient power and area utilization. In VLSI simulations, the proposed counters are 30% faster than existing parallel counters and also consume less power than other higher order counters. Additionally, using the proposed counters in existing counter-based Wallace tree multiplier architectures reduces latency and power consumption for 64 and 128-bit multipliers.

An enzyme-free colorimetric biosensing strategy for ultrasensitive and specific detection of microRNA based on mismatched stacking circuits

A novel colorimetric biosensing strategy, employing coupling spontaneous cascade catalytic hairpin assembly (CHA) circuits and mismatched hairpin, has been developed successfully for ultrasensitive and specific detection of target microRNA (miRNA). This system is composed of two layers of CHA. While target miRNA exists, the toehold-based assembly of the first-layer hairpins comes into being, followed by the generation of the first-layer CHA products and the cyclic release of the target miRNA. Then the first-layer CHA products can act as initiator for the assembly of the second-layer hairpins to produce the second-layer CHA products, with the first-layer CHA products recovered simultaneously. Finally, the second-layer CHA products can combine with hemin to form G-quadruplex/hemin DNAzyme, a well-known horseradish peroxidase (HRP) mimic, for catalyzing a colorimetric reaction. Under the optimal experimental conditions, the established biosensor can detect target miRNA down to 36.2 fM (S/N = 3) with a linear range from 100 fM to 10 nM, and discriminate target miRNA from mismatched miRNA with high selectivity. It was also applied to test the concentration of miRNA spiked into salmon sperm samples. Therefore, this biosensing strategy may become an alternative tool for the detection of miRNA in biomedical research.

Simulation of an electric behavior of the CDI system

A relatively young technology based on capacitive deionization (CDI) is known to be environmentally friendly, energy efficient and economical. In our previous work, we were able to recover almost 70% of energy by solely controlling the circuit connections of the CDI systems. However, details on the energy loss due to external resistance and other contributing factors including the power supply and the circuit connections to current collectors were not explored. The electric background wherein the uni-polar circuit connection seemed to exhibit higher charging resistance compare to bi-polar circuit, was also unknown. Thus, the electrical behavior of a CDI single-unit cell, uni- and bi-polar circuit stack systems, and energy recovering system were evaluated to understand the electric behavior during charge/discharge process.

Self-Patterning of Silica/Epoxy Nanocomposite Underfill by Tailored Hydrophilic-Superhydrophobic Surfaces for 3D Integrated Circuit (IC) Stacking

As microelectronics are trending toward smaller packages and integrated circuit (IC) stacks nowadays, underfill, the polymer composite filled in between the IC chip and the substrate, becomes increasingly important for interconnection reliability. However, traditional underfills cannot meet the requirements for low-profile and fine pitch in high density IC stacking packages. Post-applied underfills have difficulties in flowing into the small gaps between the chip and the substrate, while pre-applied underfills face filler entrapment at bond pads. In this report, we present a self-patterning underfilling technology that uses selective wetting of underfill on Cu bond pads and Si3N4 passivation via surface energy engineering. This novel process, fully compatible with the conventional underfilling process, eliminates the issue of filler entrapment in typical pre-applied underfilling process, enabling high density and fine pitch IC die bonding.

Designing Thin, Ultrastretchable Electronics with Stacked Circuits and Elastomeric Encapsulation Materials.

Many recently developed soft, skin-like electronics with high performance circuits and low modulus encapsulation materials can accommodate large bending, stretching, and twisting deformations. Their compliant mechanics also allows for intimate, nonintrusive integration to the curvilinear surfaces of soft biological tissues. By introducing a stacked circuit construct, the functional density of these systems can be greatly improved, yet their desirable mechanics may be compromised due to the increased overall thickness. To address this issue, the results presented here establish design guidelines for optimizing the deformable properties of stretchable electronics with stacked circuit layers. The effects of three contributing factors (i.e., the silicone inter-layer, the composite encapsulation, and the deformable interconnects) on the stretchability of a multilayer system are explored in detail via combined experimental observation, finite element modeling, and theoretical analysis. Finally, an electronic module with optimized design is demonstrated. This highly deformable system can be repetitively folded, twisted, or stretched without observable influences to its electrical functionality. The ultrasoft, thin nature of the module makes it suitable for conformal biointegration.

Impact of die thinning on the thermal performance of a central TSV bus in a 3D stacked circuit

In three-dimensional integrated circuits (3DICs), aggressive wafer-thinning can lead to large thermal gradients. It is crucial to understand the interaction between process parameters, such as wafer thickness, and the temperature profile in order to design high-performance 3DICs. In this paper we examine how the temperature profile of through-silicon via (TSV) bus driver/receiver cells are impacted by die thinning. While die thinning limits the ability for heat to diffuse into the wafer, it can also decrease the capacitance of the TSV which in turn decreases the driver׳s power, leading to an overall lower working temperature in some circumstances. In this work we have investigated the thermal effects of stacking 2–8 thinned ICs with TSVs, over a range of die thicknesses from 100μm to 25μm. Decreasing the die thickness from 100μm to 50μm provided the best balance with a 20% reduction in bus power at a cost of less than a 2% increase in driver temperature for all cases between 2 and 8 tiers.

A Low-Power Amplitude Modulator for QuadBand GSM/EDGE Polar Transmitter in a 65nm CMOS Process

A low power high linearity amplitude modulation path using a current reusing technique is proposed for a quad band GSM/EDGE polar transmitter. In order to reduce the current consumption and silicon area, the function of a programmable gain amplifier, AM-PM combiner and driver amplifier is realized as one stacked circuit structure. The proposed amplitude modulator is implemented in a 65nm CMOS technology and demonstrates the output power of 4 dBm and -172 dBc/Hz output noise floor level at 20 MHz offset frequency of at GSM mode. Also, the 3rd-order InterModulation Distortion (IMD3) level is below -40 dBc at all GSM/EDGE bands. The total 42 dB gain control range with a 1 dB step is achieved using a current cancelling technique without its other performance degradation. The total current consumption is 13 mA at GSM mode and 40 mA when it operates at EDGE operation from a 2.8 V supply voltage.

Solder Based Self-Assembled Structures for 3D Integration

A novel way of three dimensional (3D) chip stacking has been designed in a view to improve heat dissipation across the layers. Chip stacking using vertical interconnections forms microscale channels for coolant to circulate through the gaps. Solder-based self-assembled (SBSA) 3D structures have been designed as posts on simulated through silicon vias (TSVs) to prove the processing concept. The processing of SBSA structures using a low temperature solder alloy and dip soldering method is described. Additional processing steps to fabricate interconnected 3D structures were demonstrated. Mechanical grinding of the 3D structures shows that soldered SBSA structures were void free and robust enough to be used as a connection post for chip stacking. SBSA structures provide a solder bump that serves as a connection path in the integration of dissimilar electronic technologies. Conventional copper posts, developed in a previous project, can be an effective approach to integrated circuit (IC) stacking. However, the SBSA post provides more variety in size and shape with a potential to serve as a reservoir for solder to aid in chip bonding. The solder bumps are heat resistant and uniform thicknesses were obtained across a large array of SBSA structures. The electrical durability of SBSA posts were determined by completing I-V measurements after thermal treatments. Fabricated SBSA posts were subjected to thermal cycling with temperatures ranging from room temperature to 300 °C. The interconnected SBSA posts are shown to be stable until 165 °C with little variation in measured resistance.

Demonstration of electrical connectivity between self-assembled structures

A novel way of three dimensional (3D) chip stacking has been designed in a view to improve heat dissipation across the layers. Solder-based self assembled (SBSA) structures have been designed as 3D posts on simulated through silicon vias to demonstrate the concept. The fabrication of SBSA structures using a low temperature solder alloy and dip soldering method is described. Previously, two types of soldering—face soldering and edge soldering—were studied to fabricate SBSA structures. Face soldering refers to deposition of solder on the complete metal face whereas edge soldering refers to selective deposition of solder on only the edges of the metal face. Mechanical grinding of the 3D structures shows that face soldered SBSA structures were void free and robust enough to be used as a connection post for chip stacking. Edge soldered SBSA structures collapsed when grinding was performed. This suggests the edge soldered 3D structure may only be partially filled. Face soldered SBSA structures provide a solder bump that serves as a connection path in the integration of dissimilar electronic technologies. Cylindrical copper posts, developed in a previous project, can be an effective approach to integrated circuit stacking. However, the SBSA post provides more variety in size and shape and can serve as a reservoir for solder to aid in chip bonding. The solder bumps are heat resistant, and uniform thicknesses were obtained across a large array of SBSA structures. The electrical durability of SBSA posts were determined by completing I-V measurements after thermal treatment. SBSA posts were subjected to thermal cycling with temperatures ranging from room temperature to 300 °C. The interconnected SBSA posts are shown to be stable until 165 °C with little variation in measured resistance.