Design and Analysis of a Low Power Binary Counter-based Approximate Multiplier Architecture

Abstract

Multiplication has become the fundamental arithmetic operation in modern electronic world. Many researches in Signal processing and image processing applications are looking for energy efficient architectures. These applications exhibit error tolerance thus laying foundation for approximation techniques. The proposed work utilizes a new binary counter for partial product accumulation in a segmentation based approximate multiplication technique. The fundamental building block of the counter is a 3-bit stack circuit, which combines each of “Logic 1” bits collectively, after which a stacking process is done to convert two 3-bit modules into a 6-bit stack module. The counter circuit is obtained by converting the bit stacks to binary counts, without any XOR gates on the critical line of operation. This leads to design of binary counters with effective yield of power and delay. Moreover, applying these counters for partial product accumulation in the approximate multipliers found to be more effective when compared with conventional techniques. In future, these counter based approximate multipliers can be utilized to design energy efficient filters for image processing and signal processing applications.