A Low-Power Amplitude Modulator for QuadBand GSM/EDGE Polar Transmitter in a 65nm CMOS Process

Abstract

A low power high linearity amplitude modulation path using a current reusing technique is proposed for a quad band GSM/EDGE polar transmitter. In order to reduce the current consumption and silicon area, the function of a programmable gain amplifier, AM-PM combiner and driver amplifier is realized as one stacked circuit structure. The proposed amplitude modulator is implemented in a 65nm CMOS technology and demonstrates the output power of 4 dBm and -172 dBc/Hz output noise floor level at 20 MHz offset frequency of at GSM mode. Also, the 3rd-order InterModulation Distortion (IMD3) level is below -40 dBc at all GSM/EDGE bands. The total 42 dB gain control range with a 1 dB step is achieved using a current cancelling technique without its other performance degradation. The total current consumption is 13 mA at GSM mode and 40 mA when it operates at EDGE operation from a 2.8 V supply voltage.