Abstract

In this paper, a dual-band enhanced harmonic rejection filter along with a quadrature modulator is designed and fabricated in 0.25/spl mu/m CMOS process. This filter is simply a Sallen-Key low pass filter with transmission zeros to provide additional harmonic rejection. The measurement results that the filter significantly suppresses the unwanted harmonics generated by the modulator by more than 30 dB and 40 dB in GSM mode and DCS mode, respectively. This IC operates at 2.7V with current consumption of 4.8mA and 5.7 mA in GSM and DCS mode, respectively.

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