Interface charge trapping induced flatband voltage shift during plasma-enhanced atomic layer deposition in through silicon via

Abstract

A Through Silicon Via (TSV) is a key component for 3D integrated circuit stacking technology, and the diameter of a TSV keeps scaling down to reduce the footprint in silicon. The TSV aspect ratio, defined as the TSV depth/diameter, tends to increase consequently. Starting from the aspect ratio of 10, to improve the TSV sidewall coverage and reduce the process thermal budget, the TSV dielectric liner deposition process has evolved from sub-atmospheric chemical vapour deposition to plasma-enhanced atomic layer deposition (PE-ALD). However, with this change, a strong negative shift in the flatband voltage is observed in the capacitance-voltage characteristic of the vertical metal-oxide-semiconductor (MOS) parasitic capacitor formed between the TSV copper metal and the p-Si substrate. And, no shift is present in planar MOS capacitors manufactured with the same PE-ALD oxide. By comparing the integration process of these two MOS capacitor structures, and by using Elastic Recoil Detection to study the elemental composition of our films, it is found that the origin of the negative flatband voltage shift is the positive charge trapping at the Si/SiO2 interface, due to the positive PE-ALD reactants confined to the narrow cavity of high aspect ratio TSVs. This interface charge trapping effect can be effectively mitigated by high temperature annealing. However, this is limited in the real process due to the high thermal budget. Further investigation on liner oxide process optimization is needed.