Threshold Voltage Stability Research Articles

Suppression of boron penetration in p-channel MOSFETs using polycrystalline Si/sub 1-x-y/GexCy gate layers

Boron penetration through thin gate oxides in p-channel MOSFETs with heavily boron-doped gates causes undesirable positive threshold voltage shifts. P-channel MOSFETs with polycrystalline Si/sub 1-x-y/Ge/sub x/C/sub y/ gate layers at the gate-oxide interface show substantially reduced boron penetration and increased threshold voltage stability compared to devices with all poly Si gates or with poly Si/sub 1-x/Ge gate layers. Boron accumulates in the poly Si/sub 1-x-y/Ge/sub x/C/sub y/ layers in the gate, with less boron entering the gate oxide and substrate. The boron in the poly Si/sub 1-x-y/Ge/sub x/C/sub y/ appears to be electrically active, providing similar device performance compared to the poly Si or poly Si/sub 1-x/Ge/sub x/ gated devices.

Electroluminescence with high and stable quantum efficiency and low threshold voltage from anodically oxidized thin porous silicon diode

Highly efficient electroluminescence (EL) is obtained at low operating voltage (<5 V) from n+-type silicon-electrochemically oxidized thin porous silicon–indium–tin–oxide junctions. Continuous wave external quantum efficiency greater than 1% and power efficiency of 0.37% have been achieved. Considerable reduction of leakage current accounts for the enhancement of EL efficiency upon oxidation. The EL time response (≈30 μs) is slower than the photoluminescence one, due to slow electrical charging of porous silicon. No degradation of quantum efficiency is observed during operation and upon aging. This is attributed to the electrochemically grown oxide, which should provide a better surface passivation than the initial hydrogen coverage.

Electron emission from diamond thin films deposited by microwave plasma-chemical vapor deposition method

Abstract Diamond films with different crystal structures, morphologies and surface characteristics were synthesized under various deposition parameters and annealing conditions by the microwave plasma chemical vapor deposition (MWPCVD) method using gas mixtures of CH4, CO and H2. The effects of CH4 concentrations, grain sizes, grain orientations, film thicknesses and annealing technologies in various ambient gases on planar electron emission of diamond films were studied. The results show that small-grained and (011)-oriented diamond films deposited under the condition of high CH4 concentration present the properties of high emission current and low threshold voltage; the emission current increases with decreasing the film thickness. There are largest current density and lowest threshold voltage at the film thickness of 1.5 μm. The annealing in H2 after deposition appears to be more beneficial in lowering the threshold voltage, increasing emission current and improving stability for electron emission of films than annealing in N2 or Ar. These results indicate that diamond thin films with high emission current, low threshold voltage and high stability can be obtained by selecting suitable deposition parameters of diamond films.

Electrical properties of ZrO2 gate dielectric on SiGe

We report the electrical properties of a high dielectric constant (high-k) material, ZrO2, deposited directly on SiGe, without the use of a Si buffer layer or a passivation barrier. ZrO2 thin films of equivalent oxide thickness (EOT) down to 16.5 Å were deposited on strained SiGe layers by reactive sputtering. Results indicate that ZrO2 films on SiGe have good interfacial properties and low leakage currents. Sintering in forming gas at 350 °C for 1 h could further improve the film quality. Although threshold voltage stability and dielectric dispersion become a concern for thick ZrO2 films, thin ZrO2 films of EOT less than 20 Å exhibit excellent electrical properties making them a good candidate for SiGe applications.

Comparative evaluation of Ti salicide and Co salicide processes for CMOS devices

Optimized Ti salicide and Co salicide module processes were comparatively evaluated. The pre-amorphization process and Si intermixing process for TiSi2 formation were effective methods for maintaining low sheet resistance in narrow regions. However, in the case of the Si intermixing process, the threshold voltage of PMOS devices was unstable. With the pre-amorphization process for Ti salicide, a stable threshold voltage was obtained in CMOS devices. In addition, a low sheet resistance in the narrow regions was maintained in the Co salicide process, without the pre-amorphization process. In the contact process, CoSi2 was not easily etched off by the dry etching gas used for contact hole formation. By using the optimized pretreatment method with low sputtering yield, Co salicide will have wider process windows than Ti salicide. © 1998 Scripta Technica, Electron Comm Jpn Pt 2, 81(8): 26–31, 1998

Optimization of Program Threshold Window from Understanding of Novel Fast Charge Loss in Nonvolatile Memory

This paper describes and discusses intensively the charge loss characteristics in the stacked-gate memory device with interpoly oxide-nitride-oxide (ONO) dielectric at elevated temperatures. There exist two distinct phases in the charge loss characteristics. The dominant mechanism in the first phase can be described as the charge transport in the nitride layer. The second phase is dominated by effective thermionic emission effect from the stacked gate system. A linearly proportional relationship is also observed between normalized charge loss in the first phase and initial threshold voltage shift. Due to the fast charge loss rate, the charge loss in the first phase governs the threshold instability of the stacked-gate device. A method to determine the programming window for better threshold voltage stability based on charge loss in first phase is proposed.

Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices

This paper describes the scaling limitation factors of ONO interpoly dielectric thickness, mainly considering the charge retention capability and threshold voltage stability for nonvolatile memory cell transistors with a stacked-gate structure, based on experimental results. For good intrinsic charge retention capability, either the top- or bottom-oxide thickness should be greater than around 6 nm. On the other hand, a thicker top oxide structure is preferable to minimize degradation due to defects. It has been confirmed that a 3.2 nm bottom-oxide shows detectable threshold voltage instability, but 4 nm does not. Effective oxide thickness scaling down to around 13 nm should be possible for flash memory devices with a quarter-micron design rule.

Vertical-cavity surface-emitting lasers with thermally stable electrical characteristics

Vertical-cavity surface-emitting lasers (VCSELs) with thermally stable electrical characteristics, including slowly changing operating voltages and series resistance, have been achieved over a wide temperature range between 100 and 380 K. A stable and low threshold voltage (1.9 V at 300 K to 3.0 V at 100 K) results from the temperature insensitive carrier transport across the continuously graded heterojunction interfaces of a distributed Bragg mirror, and from the very low series resistance that has been achieved by reducing the spreading resistance of the VCSEL.

High temperature pulsed and continuous-wave operation and thermally stable threshold characteristics of vertical-cavity surface-emitting lasers grown by metalorganic chemical vapor deposition

A systematic and comparative study of the temperature performance of vertical-cavity surface-emitting lasers (VCSELs) is presented to discuss how thermal effects govern their temperature range for cw operation. These include the temperature-induced detuning of the lasing mode from the gain peak, thermal self-heating, and thermal runaway. The power dissipation of the VCSELs and the resultant rise in junction temperature have been measured as a function of the mode detuning. It is shown that low power dissipation is achieved by aligning the cavity mode to the gain peak and introducing continuously graded heterointerfaces throughout the VCSEL structure. By selecting the optimal mode detuning, VCSELs have achieved excellent operating characteristics over a broad range of temperatures, including thermally stable threshold voltage and current, and a very wide temperature range for both pulsed (100–580 K) and continuous-wave (100–400 K) operations.

Offset Trench Isolation

Feasibility of a new, recessed isolation technique that utilizes an offset, shallow trench in combination with thermal oxidation for achieving near zero final encroachment with excellent planarity is demonstrated. Etch of the shallow trench is offset from the original hardmask by an oxide sidewall spacer. After trench etch, HF is used to remove the hardmask oxide and sidewall spacers and to form a cavity which is self‐aligned to the nitride edge. Exposed silicon regions are then reoxidized and encapsulated with polysilicon. Field oxide is then grown. The final field oxide profile exhibits steep sidewall angles without inducing substrate defects as evidenced by low diode leakage. Other isolation sensitive device parametrics such as gate oxide quality and metal oxide semiconductor field effect transistor threshold voltage stability are presented and exhibit good characteristics.

Low-voltage driven ZnS:Mn MIS and MISIM thin film electroluminescent devices with Eu2O3 insulator layer

AC thin film electroluminescent devices of MIS and MISIM have been fabricated with a novel dielectric layer of Eu2O3 as an insulator. The threshold voltage for light emission is found to depend strongly on the frequency of excitation source in these devices. These devices are fabricated with an active layer of ZnS:Mn and a novel dielectric layer of Eu2O3 as an insulator. The observed frequency dependence of brightness-voltage characteristics has been explained on the basis of the loss characteristic of the insulator layer. Changes in the threshold voltage and brightness with variation in emitting or insulating film thickness have been investigated in metal-insulator-semiconductor (MIS) structures. It has been found that the decrease in brightness occurring with decreasing ZnS layer thickness can be compensated by an increase in brightness obtained by reducing the insulator thickness. The optimal condition for low threshold voltage and higher stability has been shown to occur when the active layer to insulator thickness ratio lies between one and two.

Microstructure of high temperature annealed SIMOX wafer

High temperature annealing at 1350°C is performed for SIMOX wafers to obtain a high quality thin SOI structure. After the annealing, the buried oxide has sharp interfaces within the two lattice spacings of Si(200), and oxygen precipitates are removed from the top silicon layer. MOSFET's fabricated in the SIMOX wafer with the top silicon layer 70 nm thick exhibit a good stability of threshold voltage with channel lengths down to 0.7 μm.

Boron diffusion within TaSi2 /poly-Si gates

The redistribution of boron implanted into TaSi2 /poly‐Si gates after high temperature anneals has been investigated as a function of the implantation dose and energy as well as the implantation scheme, i.e., boron implantation either into the silicide or into the poly‐Si prior to TaSi2 deposition. Implantation and diffusion profiles were obtained by means of secondary ion mass spectrometry whereas the electrical characterization of the resulting structures was performed using high‐frequency capacitance–voltage measurements. The results indicate that boron can easily diffuse from TaSi2 into poly‐Si and vice versa at 900 °C. Independent of the implantation scheme, the boron concentration within poly‐Si was found to saturate at ∼1×1019 at/cm3 for boron doses >5×1014 at/cm2. The excess of boron always accumulates within the silicide. The solubility limit of boron within TaSi2 was estimated to be >3.5×1020 at/cm3. Boron concentrations of ∼1×1019 at/cm3 within poly‐Si were found to be sufficient to realize p+ ‐polycide gates with stable and reproducible threshold voltages similar to p+ ‐poly‐Si gates. The observed boron redistribution behavior within the polycide is discussed in terms of combined lattice and grain boundary diffusion as well as grain boundary segregation.

Performance Advantages of Submicron Silicon-On-Insulator Devices for ULSI

AbstractIn this paper the various performance advantages of SOI and SOS structures for submicron ULSI circuits will be described. In addition to the traditional speed and radiation-hardness advantages, there are several significant advantages of thin-film SOI compared to bulk structures for the submicron scaling of MOS transistors. These advantages include short-channel threshold voltage stability, improved sub-threshold slope, increased saturation current, and reduced hot electron effects. Both theory and data from several groups will be presented to illustrate these effects. Since these advantages all fall in areas that are critical limits to device engineering and scaling in the submicron regime, the motivation for using SOI should be even stronger as devices are scaled to smaller dimensions in the future. Consideration of SOI or SOS on the ULSI scale will require a technology capable of low defect films with a film thickness of 1000 A or less, however. The prospects for minority carrier devices such as bipolar transistors for BI-MOS will also be discussed. Both device structure (lateral vs. vertical) and material quality are issues that must be addressed.

TaSi2gate for VLSI CMOS circuits

It is shown, that lateral shrinkage of 2-µm CMOS devices and reduction of the gate oxide thickness to about 20 nm is significantly facilitated by replacing the n+-poly-Si or polycide gates by TaSi 2 . Due to its higher work function, TaSi 2 allows the simultaneous reduction of the channel doping in the n-channel and the charge compensation in the p-channel without changing the threshold voltages. Thus compared with n+-poly-Si gate n-channel transistors substrate sensitivity and substrate current are reduced, and low-level breakdown strength is raised. In p-channel transistors, the subthreshold current behavior and U T (L)-dependence are improved. Consequently, the channel length of both n- and p-channel transistors can be reduced by about 0.5 µm without significant degradation. The MOS characteristics N ss , flatband and threshold voltage stability, and dielectric strength appear similar for TaSi 2 and n + -poly Si gate transistors.

Recoverable ionic contaminant induced failures on n-channel memory products

For an n-channel MOSFET device technology, thick oxide threshold voltage degradation on a device adjacent to a thin oxide device with exposed gate oxide and tapers frequently causes chip failure. If the thin gate oxide and tapers are completely covered, then threshold voltage stability can be attained using phosphosilicate glass to getter ionic contaminants. A first order theory is proposed that relates circuit topology, electrical requirements, and ionic contaminant drift in oxides to chip failure. The model predicts the hierarchy of failing circuits within a chip and the recovery of these failures when left on temperature-bias testing. The latter implies that burn-in conditions must be carefully chosen to avoid recovery during temperature-bias testing. Failure to do so will allow this failure mode to go undetected and result in overly optimistic reliability projections for application conditions.

Threshold Voltage Degradation of MNOS FET Devices

A film of deposited on thermally grown was studied to determine the effect that charge accumulation at the deposited film interface has on threshold voltage stability. shifts under bias and temperature result from this charge accumulation at the nitride‐oxide interface. In addition to this charge buildup‐related shift, the second mechanism causing the enhanced shift in is found to occur on long‐time, bias‐temperature stress. This second mechanism is proportional to the square root of biasing time and is exponentially dependent on temperature. The activation energy is found to be . Positive ionic drift is suggested as the mechanism causing this enhanced .

Stability of MOSFET Devices with Phosphorus‐Doped Oxide as Gate Dielectric

An experimental technique of phosphorus doping into oxide is described. Evaluation of the effectiveness of these films is made by studying bias, temperature, and time dependence of the threshold voltage stability of MOSFET devices fabricated using this phosphorus‐doped oxide as gate dielectric. Experimental data is analyzed in the light of two mechanisms known to exist in such phosphosilicate glass (PSG) layers and is shown to be in good agreement with them. It is shown that the threshold voltage stability can be maintained to within 0.03V under device operating conditions with realistic contamination levels (generally ). Results also indicate that the polarizability obeys with .