Threshold Voltage Stability Research Articles

Comparison of trapped charges and hysteresis behavior in hBN encapsulated single MoS2 flake based field effect transistors on SiO2 and hBN substrates

Molybdenum disulfide (MoS2) based field effect transistors (FETs) are of considerable interest in electronic and opto-electronic applications but often have large hysteresis and threshold voltage instabilities. In this study, by using advanced transfer techniques, hexagonal boron nitride (hBN) encapsulated FETs based on a single, homogeneous and atomic-thin MoS2 flake are fabricated on hBN and SiO2 substrates. This allows for a better and a precise comparison between the charge traps at the semiconductor-dielectric interfaces at MoS2−SiO2 and hBN interfaces. The impact of ambient environment and entities on hysteresis is minimized by encapsulating the active MoS2 layer with a single hBN on both the devices. The device to device variations induced by different MoS2 layer is also eliminated by employing a single MoS2 layer for fabricating both devices. After eliminating these additional factors which induce variation in the device characteristics, it is found from the measurements that the trapped charge density is reduced to 1.9 × 1011 cm−2 on hBN substrate as compared to 1.1 × 1012 cm−2 on SiO2 substrate. Further, reduced hysteresis and stable threshold voltage are observed on hBN substrate and their dependence on gate sweep rate, sweep range, and gate stress is also studied. This precise comparison between encapsulated devices on SiO2 and hBN substrates further demonstrate the requirement of hBN substrate and encapsulation for improved and stable performance of MoS2 FETs.

Effect of High Temperature Forming Gas Annealing on Electrical Properties of 4H-SiC Lateral MOSFETs with Lanthanum Silicate and ALD SiO<sub>2</sub> Gate Dielectric

We investigated the impact of an initial lanthanum oxide (La2O3) thickness and forming gas annealing (FGA) conditions on the MOSFET performance. The FGA has been shown to dramatically improve the threshold voltage (VT) stability of 4H-SiC MOSFETs. The FGA process leads to low VT shift and high field effect mobility due to reduction of the interface states density as well as traps by passivating the dangling bonds and active traps in the Lanthanum Silicate dielectrics. By optimizing the La2O3 interfacial layer thickness and FGA condition, SiC MOSFETs with high threshold voltage and high mobility while maintaining minimal VT shift are realized.

Threshold Voltage Instability in p-GaN Gate AlGaN/GaN HFETs

We investigate the impact of the gate contact on the threshold voltage stability in p-GaN gate AlGaN/GaN heterojunction field-effect transistors with double pulse measurements on the p-GaN gate devices and device simulations. We find that, under gate stress, in the case of high-leakage Schottky contact, a negative threshold voltage shift results from hole accumulation in the p-GaN region. Conversely, in the case of low-leakage Schottky contact, hole depletion in the p-GaN region gives rise to a positive threshold voltage shift. More generally, we show that an imbalance between the hole tunneling current through the Schottky barrier and the thermionic current across the AlGaN barrier results in a variation of the total charge stored in the p-GaN region, which in turn is responsible for the observed threshold voltage shift. Finally, we present a simplified equivalent circuit model for the p-GaN gate module.

Interface trapping in (2¯01) β-Ga2O3 MOS capacitors with deposited dielectrics

The electrical properties of interfaces and the impact of post-deposition annealing have been investigated in gate oxides formed by low pressure chemical vapor deposition (LPCVD SiO2) and atomic layer deposition (Al2O3) on (2¯01) oriented n-type β-Ga2O3 single crystals. Capacitance-voltage based methods have been used to extract the interface state densities, including densities of slow ‘border’ traps at the dielectric-Ga2O3 interfaces. It was observed that SiO2-β-Ga2O3 has a higher interface and border trap density than the Al2O3-β-Ga2O3. An increase in shallow interface states was also observed at the Al2O3-β-Ga2O3 interface after post-deposition annealing at higher temperature suggesting the high temperature annealing to be detrimental for Al2O3-Ga2O3 interfaces. Among the different dielectrics studied, LPCVD SiO2 was found to have the lowest dielectric leakage and the highest breakdown field, consistent with a higher conduction band-offset. These results are important for the processing of high performance β-Ga2O3 MOS devices as these factors will critically impact channel transport, threshold voltage stability, and device reliability.

On the Mechanisms of Formation of Memory Channels and Development of Negative Differential Resistance in Solid Solutions of the ТlInТe2–ТlYbТe2 System

The behavior of an electronic subsystem is investigated in the course of formation and development of a memory channel in solid solutions of the TlInTe2–TlYbTe2 system. An analysis of the current-voltage characteristics allows getting an insight into the reason for a sharp change in electrical conductance of the specimens under study during their transition from the high-resistance to high-conductance state and the reasons for the well known instability of threshold converters, which makes it possible to design devices with high threshold voltage stability.

The Recessed Trapezoidal Groove Dual‐Gate AlGaN/GaN E‐Mode Transistor by Using Depletion Enhancement Effect

The recessed trapezoidal groove dual‐gate profile is achieved by the low power CF4 plasma etching based on the principle of ion‐scattering. The recessed trapezoidal groove dual‐gate architecture can increase the lateral broadening of depletion width, yielding the Enhancement‐mode operation. This device demonstrates a threshold voltage of 0.43 V, a maximum drain current of 480 mA mm−1 and a trans‐conductance of 308 mS mm−1. The device exhibits a low off‐state leakage current of ≈10−10 A mm−1 and gate induced drain leakage is effectively improved. An extrinsic current gain cut off frequency of 32 GHz and a maximum oscillation frequency of 65 GHz are deduced. The threshold voltage (Vth) stability of the Schottky gate HEMT is investigated. The recessed trapezoidal groove dual‐gate exhibits a small shift of Vth, which is attributed to the lateral extension of depletion region in the trapezoidal groove dual‐gate structure.

Bias Temperature Instability of Normally‐Off GaN MIS‐FET with Low‐Pressure Chemical Vapor Deposition SiNx Gate Dielectric

In this work, characterizations are conducted to investigate the threshold voltage (VTH) stability of the normally‐off GaN metal–insulator–semiconductor (MIS‐) field‐effect transistor (FET) with fully recessed gate structure and highly reliable low‐pressure chemical vapor deposition SiNx gate dielectric. We conducted bias‐temperature instability (BTI) tests under both positive and negative gate bias. We demonstrated the highly stable VTH of the high‐performance MIS‐FETs with small BTI, which benefits from the effective interfacial protection layer. More specifically, combining the BTI tests and drain current 1/f noise analysis, we present extensive investigation of the physical origins of BTI. According to the experimental evidence and analysis, we ascribe the VTH instability to the trapping/detrapping of the pre‐existing trap states located at the SiNx/GaN interface and/or in the gate dielectric.

Positive and negative threshold voltage instabilities in GaN-based transistors

This paper reviews the main mechanisms responsible for bias-temperature instability (BTI) in GaN-based high electron mobility transistors. In the first part of the article, we focus on the threshold voltage instabilities of GaN-based MIS-HEMTs submitted to positive and negative gate bias. We demonstrate that the shift in threshold voltage originates from the trapping/de-trapping of defects located at the insulator/semiconductor interface and/or in the bulk dielectric. In the second part of the paper, we describe the threshold voltage instabilities of GaN-transistors with p-GaN gate, designed specifically for normally-off operation. We present original data indicating that under positive gate bias these devices with p-GaN gate may show a negative threshold voltage shift, which is fully recoverable. This effect is ascribed to the injection of holes under the gate contact, and to the corresponding accumulation of positive charge, possibly at the p-GaN/AlGaN interface.The results described within this paper provide an up-to-date description of the most relevant trapping processes that impact on the stability of threshold voltage and on-resistance in GaN-based transistors.

(Invited) SiC MOSFET Reliability and Implications for Qualification Testing

There are a number of potential reliability issues associated with SiC power MOSFETs, including threshold-voltage stability, gate-oxide reliability, body-diode robustness, short-circuit current robustness, and radiation effects. This talk is primarily focused on threshold-voltage stability and the need for an improved test method to unambiguously separate out good devices from bad ones. Threshold-voltage stability is affected primarily by active charge traps in the near-interfacial region of the insulating gate oxide. Their close proximity to the semiconductor interface leads to a strong time dependence in the direct-tunneling mechanism in response to changes in gate bias. This time dependence is not properly accounted for in the existing test methods for assessing high-temperature gate-bias (HTGB) effects, which allow temporary removal of bias during cool down and significant un-biased delay (up to 96 hours) before the post-stress measurements are performed. However, this delay, introduced to accommodate the practical constraints of industrial testing, renders this test practically meaningless due to the significant recovery that occurs in the charge states of the near-interfacial oxide traps. This difficulty can be overcome by reapplying the gate bias for a brief period of time before measuring. Details of the nature of the near-interfacial oxide traps will be discussed, including their activation energy. All this work will be presented within the context of standards development within JEDEC, and a new SiC power-devices qualification working group.

(Invited) Charge Traps, Temperature- and Bias-Stress Stability of Alumina Dielectric / Indium Gallium Arsenide Gate Stacks

Both interface defects and border traps - charge traps in the gate oxide - influence the behavior of InGaAs metal-oxide-semiconductor (MOS) devices. This presentation will summarize the different effects of interface and border traps on the temperature- and bias-stress behavior of aluminum oxide/InGaAs MOS gate stacks, with particular emphasis on threshold voltage stability. The influence of local interface chemistry and the complex role of hydrogen as a defect passivant are highlighted. In one set of experiments, a temperature dependent border trap response for Al2O3 gate dielectrics is investigated. This behavior is unexpected for defects that have typically been reported to charge and discharge through direct tunneling of electrons from the n-type substrate. Temperature dependent border trap frequency dispersion of the accumulation capacitance and conductance is found to be correlated with the presence of a defective interfacial layer, which can be intentionally produced either by excessive exposure to hydrating or oxidizing species during atomic layer deposition of Al2O3 or by use of a previously-reported aqueous HCl wet clean of the InGaAs surface prior to ALD. These results point out the sensitivity of the temperature dependence of the border trap response in metal oxide/III-V MOS gate stacks to the presence of processing-induced interface oxide layers, which alter the dynamics of carrier trapping at defects that are not located at the semiconductor interface. We also report on the effects of pre- and post-atomic layer deposition (ALD) defect passivation with hydrogen on the trap density and reliability of Al2O3/InGaAs gate stacks. Reliability is characterized by capacitance-voltage hysteresis measurements on samples prepared using different fabrication procedures and having different initial trap densities. Despite its beneficial ability to passivate both interface and border traps, a final forming gas (H2/N2) anneal (FGA) step is found to induce a significant hysteresis. This is caused by hydrogen depassivation of defects in the gate stack under bias stress, supported by the observed bias stress-induced increase of interface trap density, and strong hydrogen isotope effects on the measured hysteresis. Additional strategies, beyond hydrogen annealing, for more stable interface defect passivation on InGaAs will be discussed briefly.

(Invited) Room Temperature Aging Effect Improvement for Device Stability and Manufacturability of FinFET Technologies

In CMOS manufacturing industry, device threshold voltage (Vt) stability is a pre-requisite for volume manufacturing. Device architectural elements, process parameters and room temperature aging (Q-time) are the main source of Vt instability. In FinFET technology with metal/high-K gate, device Vt is controlled through effective work function engineering by optimal metal layer thickness as well as controlled Aluminum (Al) doping/diffusion within the gate stack [1-4]. The device Vtcan also be influenced by its architectural elements and process parameters [5] which should be well controlled during the volume manufacturing. However, room-temperature Q-time effects at several stages of the manufacturing process are practically unavoidable. This work demonstrates post n-work function (WF) deposition Q-time impact on device Vt instability. Longer Q-time induced Vt shifts that are independent of gate length and number of fins, as seen in Figure 1. The root cause investigations were performed using device characterization followed by elemental analysis of the gate stack (Figure 2). It was found that, the content of oxygen (O2) and Al in the gate stack is well correlated to post n-WF deposition Q-time. The device Vt instability can be explained by oxygen incorporation due to n-WF layer oxidation during the Q-time post n-WF deposition and the corresponding reduction of Al diffusion into the high-K capping layer [2, 6]. In this work, n-WF layer thickness/composition was optimized to enable immunity to a larger Q-time limit for volume manufacturing, as demonstrated in Figure 3 from n-WF layer recipe group A to group C. The reliability impact of the gate stack was also assessed. Device benefits such as Tinv scaling and thereby Ion-Ioffperformance improvement was also demonstrated without compromising the reliability. Reference [1] L.P.B. Lima et al, J. Appl. Phys., 115, 074504, 2014 [2] A. Veloso et al, Jpn. J. Appl. Phys.52. 04CA02, 2013 [3] L. Kornblum et al, Appl. Phys. Lett., 100, 062907, 2012 [4] C.L. Hinkle et al, Appl. Phys. Lett.,96, 103502, 2010 [5] M. Togo et al, VLSI tech. Symp. Dig.pp. 140-141, 2014 [6] A. Veloso et al, VLSI Tech. Symp. Dig. pp. 34-35, 2011. Figure 1

(Invited) Room Temperature Aging Effect Improvement for Device Stability and Manufacturability of FinFET Technologies

In FinFET technology, device threshold voltage (Vt) stability is a pre-requisite for volume manufacturing. Device architectural elements, process parameters and room temperature aging (Q-time) are the main source of Vt instability. For the first time, we report a method to minimize Vt instability due to Q-time in gate stack work function (n-WF) layer film depositions. Underlying mechanism was investigated using elemental analysis. The optimized n-WF layer recipes were developed that are less sensitive to the Q-time. Device benefits such as Tinv scaling and thereby Ion-Ioff performance improvement is demonstrated without compromising the reliability.

Design and simulation of a novel E-mode GaN MIS-HEMT based on a cascode connection for suppression of electric field under gate and improvement of reliability**Project supported by the Key Technologies Support Program of Jiangsu Province (No. BE2013002-2) and the National Key Scientific Instrument and Equipment Development Projects of China (No. 2013YQ470767).

We proposed a novel AlGaN/GaN enhancement-mode (E-mode) high electron mobility transistor (HEMT) with a dual-gate structure and carried out the detailed numerical simulation of device operation using Silvaco Atlas. The dual-gate device is based on a cascode connection of an E-mode and a D-mode gate. The simulation results show that electric field under the gate is decreased by more than 70% compared to that of the conventional E-mode MIS-HEMTs (from 2.83 MV/cm decreased to 0.83 MV/cm). Thus, with the discussion of ionized trap density, the proposed dual-gate structure can highly improve electric field-related reliability, such as, threshold voltage stability. In addition, compared with HEMT with field plate structure, the proposed structure exhibits a simplified fabrication process and a more effective suppression of high electric field.

High Threshold Voltage Uniformity and Low Hysteresis Recessed-Gate Al2O3/AlN/GaN MISFET by Selective Area Growth

In this paper, a normally off Al2O3/AlN/GaN MISFET on Si substrate for achieving high threshold voltage stability and uniformity is obtained based on selective area growth. A thin AlN space layer (SL, ~1 nm) is adopted to GaN-based template, and the AlGaN/GaN het-erostructureis selectivelygrownon the template to naturally form a recessed structure. By insertion of the AlN SL, the Al2O3/AlN/GaN interface trapping and scattering effects are effectively suppressed. As a result, a low threshold voltage hysteresis ( $\Delta {V}_{\mathrm{ th}}$ , 80 mV at maximum gate sweep voltage of 10 V by dc ${I}$ – ${V}$ measurement and smaller than 200 mV in linear region by pulse ${I}$ – ${V}$ measurement) and a high peak field-effect mobility ( $\mu _{\sf FE})$ of 192 cm2/ $\text{V}\cdot \text{s}$ are obtained in Al2O3/AlN/GaN MISFET. It is a significant improvement compared with Al2O3/GaN MISFET without AlN SL. The Al2O3/AlN/GaN MISFET also exhibits a maximum drain current ( ${I}_{d,max})$ of 620 mA/mm, a low on-resistance ( ${R}_{\rm {ds}, \mathrm{\scriptscriptstyle ON}})$ of $9.6~\Omega \cdot $ mm, and a high uniformity of ${V}_{\mathrm{ th}}$ (2.5 ± 0.1 V).

Investigation of <italic>In Situ</italic> SiN as Gate Dielectric and Surface Passivation for GaN MISHEMTs

In this paper, we present a systematic investigation of metal–organic chemical vapor deposition-grown in situ SiN as the gate dielectric and surface passivation for AlGaN/GaN metal insulator semiconductor high electron mobility transistors (MISHEMTs). The dielectric constant and breakdown field of the in situ SiN were extracted from devices with varied gate dielectric thicknesses. Using frequency-dependent capacitance–voltage and parallel conductance methods, we obtained a low trap density of $\sim 3\times 10^{12}$ cm $^{-2}$ eV $^{-1}$ at the SiN/AlGaN interface. The MISHEMTs with a source–drain distance of $3~\mu \text{m}$ show a maximum drain current of 1560 mA/mm and a high on/off current ratio of $10^{9}$ . The device threshold voltage ( ${V}_\textsf {th}$ ) stability was assessed by means of both negative and positive gate stress measurements, as well as temperature-dependent $ {I}_\textsf {D}$ – ${V}_\textsf{G}$ measurements. We observed a minimal $ {V}_\textsf{th}$ shift of ~0.4 V under both 3000 s gate stress of ${V}_\textsf {GS}= 4$ V and up to 200 °C thermal stimulation. Furthermore, combining the in situ SiN with plasma-enhanced chemical vapor deposition SiN, we developed a bilayer passivation scheme for effective suppression of current collapse. Employing the high-quality in situ SiN, we have demonstrated large-area GaN MISHEMTs on Si with a gate width of 20 mm, showing a low off-state leakage of $2~\mu \text{A}$ /mm at 600 V and a low dynamic/static ON-resistance ratio. The device results show great advantages of employing in situ SiN in D-mode GaN MISHEMTs for high-efficiency power switching applications.

Al-implanted on-axis 4H-SiC MOSFETs

In this paper, the impact of temperature and time stress on gate oxide stability of several multi-implanted and epitaxied 4H-SiC nMOSFET is presented. The oxide layer was processed under a rapid thermal process (RTP) furnace. The variation of the main electrical parameters is shown. We report the high quality and stability of such implanted MOSFETs, and point out the very low roughness effect of the on-axis-cut sample. Particularly, in the best case, effective channel mobility (μfe) overcomes 20 cm2.V−1.s−1 at 300 °C for a channel length of 12 μm, which is very encouraging for implantation technology. Starting from 200 °C, the apparent increase of the μfe peak of the MOSFET ceases and tends to saturate with further temperature increase. This is an indication of the potential of MOSFETs built on on-axis substrates. Thus, starting from the real case of an implanted MOSFET, the global purpose is to show that the electrical performance of such an on-axis-built device can tend to reach that of the ideal case, i.e. epitaxied MOSFET, and even overcome its electrical limitation, e.g. in terms of threshold voltage stability at high temperature.

Technology and Reliability of Normally-Off GaN HEMTs with p-Type Gate

GaN-based transistors with p-GaN gate are commonly accepted as promising devices for application in power converters, thanks to the positive and stable threshold voltage, the low on-resistance and the high breakdown field. This paper reviews the most recent results on the technology and reliability of these devices by presenting original data. The first part of the paper describes the technological issues related to the development of a p-GaN gate, and the most promising solutions for minimizing the gate leakage current. In the second part of the paper, we describe the most relevant mechanisms that limit the dynamic performance and the reliability of GaN-based normally-off transistors. More specifically, we discuss the following aspects: (i) the trapping effects specific for the p-GaN gate; (ii) the time-dependent breakdown of the p-GaN gate during positive gate stress and the related physics of failure; (iii) the stability of the electrical parameters during operation at high drain voltages. The results presented within this paper provide information on the current status of the performance and reliability of GaN-based E-mode transistors, and on the related technological issues.

Integration of Gate Recessing and <italic>In Situ</italic> Cl− Doped Al2O3 for Enhancement-Mode AlGaN/GaN MOSHEMTs Fabrication

This letter demonstrates an integration process of in situ Cl− doped Al2O3 and gate recess technique to fabricate the enhancement mode AlGaN/GaN MOSHEMTs. The Cl− doped Al2O3 thin film is deposited by the ultrasonic spray pyrolysis deposition and characterized by transmission electron microscopy and X-ray photoelectron spectroscopy. The relative permittivity of Cl− doped Al2O3 is higher than the pure Al2O3 and the output current is enhanced. The threshold voltage of the enhancement mode AlGaN/GaN MOSHEMT with the Cl− doped Al2O3 gate dielectric layer rose from 0.2 to 1.3 V. Furthermore, the breakdown voltage of present enhancement mode AlGaN/GaN MOSHEMT reached 650 V. It was also found that the MOSHEMT with Cl− doped Al2O3 has higher gate leakage than that with pure Al2O3. The thermal stability of threshold voltage and current collapse phenomenon is described in this letter.

High operational and environmental stability of high-mobility conjugated polymer field-effect transistors through the use of molecular additives.

Due to their low-temperature processing properties and inherent mechanical flexibility, conjugated polymer field-effect transistors (FETs) are promising candidates for enabling flexible electronic circuits and displays. Much progress has been made on materials performance; however, there remain significant concerns about operational and environmental stability, particularly in the context of applications that require a very high level of threshold voltage stability, such as active-matrix addressing of organic light-emitting diode displays. Here, we investigate the physical mechanisms behind operational and environmental degradation of high-mobility, p-type polymer FETs and demonstrate an effective route to improve device stability. We show that water incorporated in nanometre-sized voids within the polymer microstructure is the key factor in charge trapping and device degradation. By inserting molecular additives that displace water from these voids, it is possible to increase the stability as well as uniformity to a high level sufficient for demanding industrial applications.

Gate dielectric ion implantation to modulate the threshold voltage of In2O3 nanowire field effect transistors

In semiconductor technology, In2O3 nanowire field effect transistor (FET) can serve as an important building block due to its admirable electrical switching properties. However, the relatively too large threshold voltages and threshold voltage fluctuations of the devices may hinder their extensive applications. In this report, N+ ion implantation of gate dielectric was conducted to modulate the threshold voltage of In2O3 nanowire FET. Electrical measurements reveal that the threshold voltage can be reduced to as low as −2.0 V from the initial −23.2 V after ion implantation. This can be attributed to the effects of implantation induced electron traps. Moreover, it is found that the stability of threshold voltage can be improved by ion implantation. This simple and convenient method indicates that gate dielectric ion implantation may be a potential way to realize the low voltage operation and uniform In2O3 nanowire FETs.