Threshold Voltage Stability Research Articles

Charge trapping gate stack enabled non-recessed normally off AlGaN/GaN HEMT with high threshold voltage stability

This paper reports a non-recessed normally off AlGaN/GaN high-electron-mobility transistor (HEMT) with a charge trapping gate dielectric stack. The charge trapping gate dielectric stack featuring a low density of fixed positive charges consists of an O3-based Al2O3 tunneling layer and an O3-based HfO2 blocking layer, both deposited via atomic layer deposition. For HEMT with a 15 nm AlGaN barrier layer, a threshold voltage of 2.57 V and an on-resistance of 8.50 Ω × mm are achieved. For positive bias temperature instability (PBTI) testing, the electric field provided by the 15 nm AlGaN layer serves as a barrier to channel carriers, significantly enhancing the PBTI test stability. The optimized gate dielectric stack enables the fabrication of the non-recessed normally off metal–insulator–semiconductor-HEMT with enhanced threshold voltage (Vth) stability.

Dynamic Bias-Temperature Instability Testing in SiC MOSFETs

For power converter development in mission critical applications, the attractive performances of SiC power MOSFETs are shadowed by reliability concerns, particularly those induced by the defects at the gate dielectric. Charge trapping at the oxide-semiconductor interface can lead to threshold voltage drift, degrading the power converter efficiency and lifetime. The scope of this contribution is to show a testing methodology under development to understand SiC power MOSFET threshold voltage stability under dynamic and accelerated operating conditions. The presented testing methodology relies on switching the device under test at high-voltage and current, simultaneously applying a gate stress and extracting threshold voltage from switching transients. The paper outlines the setup description, its operating modes and intended design of experiment to assess SiC MOSFET threshold voltage stability.

Charge Trapping and Emission during Bias Temperature Stressing of Schottky Gate GaN-on-Silicon HEMT Structures Targeting RF/mm Wave Power Amplifiers.

For operation as power amplifiers in RF applications, high electron mobility transistor (HEMT) structures are subjected to a range of bias conditions, applied at both the gate and drain terminals, as the device is biased from the OFF- to ON-state conditions. The stability of the device threshold voltage (Vt) condition is imperative from a circuit-design perspective and is the focus of this study, where stresses in both the ON and OFF states are explored. We see rapid positive threshold voltage increases under negative bias stress and subsequent recovery (i.e., Vt reduces), whereas conversely, we see a negative Vt shift under positive stress and Vt increase during the subsequent relaxation phase. These effects are correlated with the thickness of the GaN layer and ultimately result from the deep carbon-acceptor levels in the C-GaN back barrier incorporated to screen the buffer between the silicon substrate and the epitaxially grown GaN layer. Methods to mitigate this effect are explored, and the consequences are discussed.

Design optimization of wide-gate swing E-mode GaN HEMTs with junction barrier Schottky gate

To increase the gate swing, a GaN-based high-electron-mobility transistor with a junction barrier Schottky gate (JBS-HEMT) was proposed. Compared to conventional p-GaN Schottky gate HEMTs (Conv-HEMT), the high electric field at the surface is transferred to the pn junction inside the body, and the extended depletion region of the pn junction shields the surface Schottky contact interface for the JBS-HEMT. After fitting the model to the reported device, the proposed JBS-HEMT was simulated and optimized using the Sentaurus TCAD tool. The simulation results of the optimized JBS-HEMT demonstrate a high gate breakdown voltage (17.6 V), which is 158.5% higher than the gate breakdown voltage of the Conv-HEMT (11.1 V) and a lower gate leakage current of six orders of magnitude than the Conv-HEMT at the gate-to-source voltage of 10 V. The proposed JBS-HEMT exhibits a positive threshold voltage (1.68 V) and excellent threshold voltage stability, and the maximum threshold voltage drift of the JBS-HEMT (+0.237 V) is smaller than that of the Conv-HEMT (−0.714 V) under gate stress conditions. The peak transconductance of the JBS-HEMT (186 mS mm−1) at athe drain-to-source voltage of 10 V showed almost no reduction compared to the Conv-HEMT (189 mS mm−1), which solves the problem of decreased transconductance capability of the reported GaN HEMT with a p-n junction gate (PNJ-HEMT). It was confirmed that the JBS-HEMT has excellent gate stability and potential for power electronics applications.

Mobility and current boosting of In-Ga-Zn-O thin-film transistors with metal capping layer oxidation

This study investigates the effect of an oxidized Ta capping layer on the boosting of field-effect mobility (μ FE) of amorphous In-Ga-Zn-O (a-IGZO) Thin-film transistors (TFTs). The oxidation of Ta creates additional oxygen vacancies on the a–IGZO channel surface, leading to increased carrier density. We investigate the effect of increasing Ta coverage on threshold voltage (V th), on-state current, μ FE and gate bias stress stability of a-IGZO TFTs. A significant increase in μ FE of over 8 fold, from 16 cm2 Vs−1 to 140 cm2 Vs−1, was demonstrated with the Ta capping layer covering 90% of the channel surface. By partial leaving the a-IGZO uncovered at the contact region, a potential barrier region was created, maintaining the low off-state current and keeping the threshold voltage near 0 V, while the capped region operated as a carrier-boosted region, enhancing channel conduction. The results reported in this study present a novel methodology for realizing high-performance oxide semiconductor devices. The demonstrated approach holds promise for a wide range of next-generation device applications, offering new avenues for advancement in metal oxide semiconductor TFTs.

Study of drain-induced channel effects in vertical GaN junction field-effect transistors

A normally-off vertical gallium nitride (GaN) junction field-effect transistor (JFET) is demonstrated in this work. The device shows an on/off current ratio of 3.6 × 1010, a threshold voltage (V TH) of 1.64 V, and a specific on-resistance (R ON,SP) of 1.87 mΩ·cm2. Drain-induced channel effects were proposed to explain the change in the gate current at different drain voltages. Drain current decline in the output characteristics and the reverse turn-on between drain and source can be explained by effects. A technological computer-aided design was used to simulate the change of the depletion region and confirm the explanation. Detailed analyses of the channel effects provide a reference for the design of novel structures. The characteristics at different temperatures demonstrated the stability of threshold voltage and specific on-resistance, thus indicating the great potential of applications in switching power circuits of vertical GaN JFETs.

Atomic Layer Deposition of WO3-Doped In2O3 for Reliable and Scalable BEOL-Compatible Transistors.

Tungsten oxide (WO3) doped indium oxide (IWO) field-effect transistors (FET), synthesized using atomic layer deposition (ALD) for three-dimensional integration and back-end-of-line (BEOL) compatibility, are demonstrated. Low-concentration (1∼4 W atom %) WO3-doping in In2O3 films is achieved by adjusting cycle ratios of the indium and tungsten precursors with the oxidant coreactant. Such doping suppresses oxygen deficiency from In2O2.5 to In2O3 stoichiometry with only 1 atom % W, allowing devices to turn off stably and enhancing threshold voltage stability. The ALD IWO FETs exhibit superior performance, including a low subthreshold slope of 67 mV/decade and negligible hysteresis. Strong tunability of the threshold voltage (Vth) is achieved through W concentration tuning, with 2 atom % IWO FETs showing an optimized Vth for enhancement-mode and a high drain current. ALD IWO FETs have remarkable stability under bias stress and nearly ideal performance extending to sub-100 nm channel lengths, making them promising candidates for high-performance monolithic 3D integrated devices.

The Enhanced Performance of Oxide Thin-Film Transistors Fabricated by a Two-Step Deposition Pressure Process.

It is usually difficult to realize high mobility together with a low threshold voltage and good stability for amorphous oxide thin-film transistors (TFTs). In addition, a low fabrication temperature is preferred in terms of enhancing compatibility with the back end of line of the device. In this study, α-IGZO TFTs were prepared by high-power impulse magnetron sputtering (HiPIMS) at room temperature. The channel was prepared under a two-step deposition pressure process to modulate its electrical properties. X-ray photoelectron spectra revealed that the front-channel has a lower Ga content and a higher oxygen vacancy concentration than the back-channel. This process has the advantage of balancing high mobility and a low threshold voltage of the TFT when compared with a conventional homogeneous channel. It also has a simpler fabrication process than that of a dual active layer comprising heterogeneous materials. The HiPIMS process has the advantage of being a low temperature process for oxide TFTs.

Suppressed current collapse and improved threshold voltage stability of AlGaN/GaN HEMT via O2 plasma treatment

A comprehensive study about the effects of O2 plasma treatment on the dynamic performance of AlGaN/GaN high electron mobility transistors (HEMTs) is presented. The drain current transient spectroscopy indicated a much decelerated and mitigated current degradation process for the HEMT with O2 plasma treatment. Upon negative gate bias stressing, current collapse of 10.7 % and minor threshold voltage shift of 0.16 V were achieved by O2 plasma treatment. In addition, current collapse ratio of the HEMTs as a function of stress/recovery time showed that the HEMT with O2 plasma treatment had a superior performance in various on-off conditions. Particularly in high-frequency switching events, current collapse ratio was reduced from about 50 % to 0.2 %. At last, the quality of AlGaN/metal interface with O2 plasma treatment is demonstrated by capacitance-frequency measurements, with the interface trap density Dit is estimated to be 1.39 × 1012 cm−2 eV−1. These results indicate that GaN HEMT with O2 plasma treatment is a promising technology in power switching applications.

Interaction of Negative Bias Instability and Self-Heating Effect on Threshold Voltage and SRAM (Static Random-Access Memory) Stability of Nanosheet Field-Effect Transistors.

In this paper, we investigate the effects of negative bias instability (NBTI) and self-heating effect (SHE) on threshold voltage in NSFETs. To explore accurately the interaction between SHE and NBTI, we established an NBTI simulation framework based on trap microdynamics and considered the influence of the self-heating effect. The results show that NBTI weakens the SHE effect, while SHE exacerbates the NBTI effect. Since the width of the nanosheet in NSFET has a significant control effect on the electric field distribution, we also studied the effect of the width of the nanosheet on the NBTI and self-heating effect. The results show that increasing the width of the nanosheet will reduce the NBTI effect but will enhance the SHE effect. In addition, we extended our research to the SRAM cell circuit, and the results show that the NBTI effect will reduce the static noise margin (SNM) of the SRAM cell, and the NBTI effect affected by self-heating will make the SNM decrease more significantly. In addition, our research results also indicate that increasing the nanosheet width can help slow down the NBTI effect and the negative impact of NBTI on SRAM performance affected by the self-heating effect.

Mg activation anneal of the p-GaN body in trench gate MOSFETs and its effect on channel mobility and threshold voltage stability

This work addresses the impact of the Mg activation anneal step and the resulting acceptor concentration on the channel mobility and VT stability of vertical MOSFETs. Increasing the annealing time with N2 only ambient and the annealing temperature with O2 in the ambient is shown to be effective in increasing the channel acceptor concentration. When the effective acceptor concentration is increased, the mobility is degraded due to a transition in the main scattering mechanism from Coulomb to surface roughness scattering. Degradation of the on-state current and maximum transconductance at high operating temperatures was linked to bulk mobility degradation of the drift layer due to lattice scattering. The two Mg activation annealing conditions considered here show different trends with regard to the threshold voltage stability, while N2 only ambient did not impact this parameter, including O2 increased threshold voltage instability. It is shown that increasing the Mg chemical concentration in the p-GaN layer degrades channel mobility and threshold voltage stability, irrespectively of the effective acceptor concentration, providing evidence for degradation of the channel/dielectric interface characteristics with higher Mg chemical concentration. This study shows that it is possible to achieve very low threshold voltage hysteresis and high channel mobility by reducing the Mg chemical concentration while maintaining high effective acceptor concentration. These results provide key insights for the development of vertical GaN FETs.

Threshold voltage uniformity improvement by introducing charge injection tuning for low-temperature poly-Si thin film transistors with metal/oxide/nitride/oxide/silicon structure

Low-temperature poly-Si thin film transistors (TFTs) with a metal/oxide/nitride/oxide/silicon structure were fabricated to investigate the feasibility of suppressing threshold voltage variations between TFTs. By applying relatively high positive and negative gate bias voltages, threshold voltage could be tuned positively and negatively, respectively, by injecting charges into the charge trap layer. Stability of threshold voltage against positive gate bias at a level close to the actual circuit operation was not degraded compared with the case of an as-fabricated TFT. A uniform threshold voltage distribution could be achieved in a preliminary test using 16 TFTs by converging threshold voltages with a target value by tuning the threshold voltage for each TFT.

Impact of post-deposition annealing on the electronic properties of Al2O3/GaN interface by first-principles study

The electronic properties of Al2O3/GaN interface are investigated by first-principles calculations to explore the effects of post-deposition annealing (PDA) in O2 or N2 ambient. It is found that for the initial Al2O3/GaN interface without post-annealing, there are traps with a wide energy range in the GaN band gap, mainly caused by dangling bonds (DBs) of Ga, Al, and N atoms. However, with proper PDA in O2 ambient, the trap states induced by Al DBs completely merge into GaN conduction band, while the trap states induced by Ga DBs and N DBs completely merge into GaN valence band. Therefore, the interface shows a cleaner band structure. Nevertheless, excessive interface O content can lead to trap states around the valence band maximum induced by N DBs and O DBs. For PDA in N2 ambient, the trap states induced by Al DBs and Ga DBs can be completely suppressed under appropriate interface N content. Unfortunately, deep and shallow traps caused by N DBs can be introduced in the GaN band gap. This study systematically reveals the physical mechanism by which PDA in O2 ambient compared to N2 can significantly reduce the interface state density and improve threshold voltage stability of the device.

Improvement in the Stability of Cation (Si)/Anion (F or N) Codoped ZnO Thin-Film Transistors Formed via Atomic Layer Deposition

The characteristics of cation (Si) and anion (F or N) codoped ZnO thin films formed via atomic layer deposition and corresponding device properties were investigated for different anion doping concentrations with a fixed Si doping amount. All films exhibited the (100) primary diffraction peak, indicating a hexagonal wurtzite structure. All codoped ZnO films exhibited the same effect of oxygen vacancy passivation, i.e., reduced oxygen vacancy. However, the electrical and optical characteristics of the films exhibited contrasting tendencies depending on the type of anion element. The optimized device properties, i.e., the subthreshold swing, field-effect mobility, threshold voltage, and bias stability were 6.62 E − 01 V/dec, 5.10 cm2/V·s, -11.16 V, and 6.32 V in the Si/F-19 condition and 5.98 E − 01 V/dec, 16.60 cm2/V·s, 1.07 V, and 0.14 V in the Si/N-19 condition, respectively. These characteristics were attributable to the correlation effects of the reduced interfacial trap density from Si doping and oxygen vacancy passivation from anion doping. Notably, the behavior of each anion was different in terms of the charge carrier concentration. First-principles calculations based on the density functional theory using the Vienna ab initio simulation package (VASP) code were performed to obtain valuable insights into the energy band structure in terms of the performance of the codoped ZnO films.

Trade-off between gate leakage current and threshold voltage stability in power HEMTs during ON-state and OFF-state stress

We present a detailed investigation of the impact of electron gate leakage on the threshold voltage stability of normally-off GaN HEMTs with p-GaN gate. The analysis is based on combined DC, pulsed and transient measurements, carried out on two test wafers with different gate processes, resulting in different levels of gate leakage current. The key results demonstrate: (a) the existence of four different charge-trapping processes, whose interplay determines the sign and amplitude of the threshold voltage variation; (b) a reasonable increase in gate leakage is beneficial for eliminating the negative threshold voltage instability under positive gate bias, and for substantially reducing the positive threshold shift under off-state stress. Furthermore, (c) we present a proper characterization methodology for device understanding.

Threshold voltage instability in SiO2-gate semi-vertical GaN trench MOSFETs grown on silicon substrate

We analyze the threshold voltage stability under positive gate stress in semi-vertical GaN trench MOSFETs with silicon oxide gate insulator. The experimental results, obtained by a fast setup capable of recording the threshold voltage transient with stress time as low as 10 μs, indicate that positive gate voltage induces a trapping of electrons in oxide border traps. In addition, experimental data obtained at different temperature and recovery bias conditions suggest that trapping proceeds through tunneling, from the inversion channel in the p-GaN layer to the traps. Finally, we developed a mathematical framework to model such tunneling process that conceptually explains the origin of the strongly stretched trapping transients and the results were compared with some relevant references on positive bias temperature instability in Si and GaN based devices.

A Conjugated Polymer Bearing Perylenediimide (PDI) and Ferrocene (Fc) Exhibiting Stable Data‐Storage Performance

AbstractPolymeric materials have been widely researched and used as active‐layers to fabricate data‐storage resistance random‐access memory (ReRAM) devices. Nevertheless, the problems as drift voltage, weak stability, and low reproducibility largely restrict their practical application in next‐generation memory systems, mainly induced by the molecular stacking defects that limited the efficient charge‐carrier migration throughout the active‐layers. Thus, how to weaken the molecular stacking defects and thus improve the overall ReRAM performance is a scientific issue that needs to be solved urgently. In this work, an organometallic polymer 5,12‐di(thiophen‐2‐l)‐2,9‐di(tridecan‐7‐yl)anthra[2,1,9‐def:6,5,10‐d'e'f']diisoquinoline‐1,3,8,10(2H,9H)‐tetraone P(DTPDI‐Fc) is designed with ferrocene (Fc) and perylenediimide (PDI) building repeats. The X‐ray diffraction (XRD) test confirms the regioregular stacking styles of P(DTPDI‐Fc) in solid states, and atomic force microscope (AFM) measurement verified the continuous and smooth surface morphology of P(DTPDI‐Fc) films. Therefore, the charge carriers can easily inject into P(DTPDI‐Fc) film and can efficiently migrate throughout P(DTPDI‐Fc) films. Thus, P(DTPDI‐Fc) devices show excellent memory behaviors with low high‐conductance state ON‐state current, stable threshold voltage, long‐time stability, and high device reproducibility. This work affords a practical strategy to weaken molecular stacking defects and to improve stacking regioregularity, which will give a guidance for the designing of multilevel data‐storage ReRAM devices in future researches.

Enhanced performances of a-IGZO TFTs with oxide passivation layers fabricated by hollow cathode assisted PLD

Pulsed laser deposition (PLD) and two-step thermal annealing are combined to fabricate MgO, TiO2, Y2O3, Al2O3, ZrO2 and HfO2 passivation layers on a-IGZO TFTs. The influences of the passivation layers on the electrical properties are investigated. It is found that conventional PLD is sufficient to deposit high-quality Y2O3 and ZrO2 passivation layers, but hollow cathode assisted PLD (HC-PLD) should be employed to solve the oxygen deficiency in MgO, TiO2, Al2O3, and HfO2 thin films by oxygen plasma. Furthermore, two-step annealing is adopted to improve the performances of the devices: Firstly, a-IGZO thin films are pre-annealed to enhance the carrier mobility. Secondly, the passivation layers are deposited on a-IGZO and the whole structures are post-annealed to endow the good on-off performance. The sharp a-IGZO/passivation interfaces remain after thermal annealing. The Hall mobility is mainly restricted by the scattering of metal ions at the a-IGZO/passivation interface. TiO2 passivated devices exhibit the highest Hall mobility of 16.7 cm2V−1s−1, owing to the smaller cation charge. The threshold voltage stability under positive gate bias is dependent on the metal-oxygen bond strength in the passivation layers. ZrO2 passivated devices have the lowest threshold voltage shift, beneficial from the strong Zr-O bonds. The subthreshold performance and the stability under illumination are determined by the oxygen vacancies at a-IGZO/passivation interfaces and ZrO2 passivated devices exhibit the lowest subthreshold swing and the best illumination stability.

Dynamic Performance Analysis of Logic Gates Based on p-GaN/AlGaN/GaN HEMTs at High Temperature

The high-temperature operation of the AlGaN/GaN high electron mobility transistors (HEMTs) and direct-coupled FET logic (DCFL) inverters, NOR gates, and NAND gates are demonstrated. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> -GaN-gate HEMTs which are used as drivers in DCFL circuits exhibit proper E-mode operation with a relatively stable threshold voltage <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> (drift -0.31 V) and high electron mobility μ of 587 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V∙S at 300 °C. The fabricated logic gates have a small switching time at room temperature (RT). As the temperature increases to 300 °C, these logic gates exhibit a slight increase in switching time, wherein the fall time and rise time of the inverter from room temperature to 300 °C increases from 16 ns to 129 ns and 128 ns to 0.864 μs, respectively. The logic gates herein exhibit accurate and stable operation at 300 °C. Furthermore, the reason for the switching time increase at high temperature is revealed from the perspective of devices.

Evolution of Interface State Density and Near Interface Oxide Traps under Controlled Nitric Oxide Annealing in SiO&lt;sub&gt;2&lt;/sub&gt;/SiC Lateral MOSFETs

In this paper, the effect of different post oxide deposition nitridation processes in NO on n-channel lateral MOSFETs fabricated on implanted 4H-SiC were investigated. In particular, the electrical behavior of the MOSFETs was deeply investigated not only in terms of SiO2/SiC interface state density and field effect mobility, but also considering the threshold voltage stability effect. The aim of this work was to explore to which extent post oxide deposition annealing in NO is beneficial for the MOS interface behavior and when their detrimental effects start to become predominant on the device performances. Here, the separation of the trapping states at the interface – either close to the conduction and valence band edges – and the near interface oxide traps are reported for the different duration of the post oxide deposition annealing. In fact, cyclic gate bias stress was employed in order to analyze the behavior of the trapping states and to correlate them with the variation of the benefits in terms of the channel mobility (that saturates at about 80 cm2V-1s-1), and on the threshold voltage instability effect. In particular, prolonged PDAs may induce an increase of the amount of trapping states close to the valence band edge and inside the insulator of about 20% and 50 %, respectively.