Threshold Voltage Stability Research Articles

Stability of nc-Si:H TFTs With Silicon Nitride Gate Dielectric

We report the fabrication and characterization of bottom-gate and top-gate nanocrystalline silicon (nc-Si:H) thin-film transistors (TFTs) with amorphous-silicon nitride (a-SiNx:H) as the gate dielectric. The devices were fabricated using standard 13.56-MHz plasma-enhanced chemical vapor deposition at 240 degC. Here, the same 80-nm nc-Si:H channel, 300-nm a-SiNx:H gate dielectric, and 60-nm n+ nc-Si:H ohmic contact layers were used in both TFT structures. We analyzed the effects of gate configuration on TFT performance and, in particular, the electrical stability. The stability tests were carried out at a gate bias stress in the range from 20 to 40 V. The nc-Si:H TFTs demonstrated much better threshold-voltage (VT ) stability compared with the amorphous-silicon (a-Si:H) counterparts, offering great promise for applications in active-matrix organic light-emitting diode (AMOLED) displays

Hot-Wire Deposited Nanocrystalline Silicon TFTs on Plastic Substrates

AbstractHot-wire chemical vapor deposition (HWCVD) technique was used to deposit nanocrystalline silicon (nc-Si) thin film transistors (TFT) on thin polyimide sheets. Two straight tantalum filaments at 1850°C with a substrate to filament distance of 4 cm was used to deposit HWCVD nc-Si with no thermal damage to plastic sheet. Top-gate staggered TFTs were fabricated at 150°C and 250°C using a HWCVD nc-Si channel, PECVD silicon nitride gate dielectric, and microcrystalline n+ drain/source contacts. Leakage current of 3.3×10-12 A, switching current ratio of 3×106, and sub threshold swing of 0.51 V/decade were obtained for TFTs with aspect ratio of 1400 µm / 100 µm fabricated at 150°C. The highest electron field effect mobility was found to be 0.3 cm2/V.s observed for TFTs deposited at lower substrate temperature. Measurements showed superior threshold voltage stability of HW nc-Si TFTs over their amorphous silicon (a-Si) counterparts.

Subthreshold Operation of a Monolithically Integrated Strained-Si Current Mirror at Low Temperatures

The dc operation of a simple current mirror built with two monolithically integrated strained-Si (s-Si) MOSFETs operating in the subthreshold region is studied as a function of temperature. At room temperature, the log-log current relationship is linear over 4 dec. The consumed power is approximately 100 muW at 300 K but only 1 nW at 160 K. The cost of this reduction in power is a reduced linear log-log current range. Reducing the temperature further increases the threshold voltage, obstructing operation below 160 K. A comparison is made with the Si control circuit, highlighting the improved linearity and the threshold voltage stability in the s-Si circuit. The estimated cutoff frequency of the subthreshold strained-Si current mirror at 300 K is 50 MHz, compared to 10 kHz for the Si MOSFETs

Charge Trapping & NBTI in High k Gate Dielectric Stacks

Over recent years, there has been increasing research and development efforts to replace SiO2 with high dielectric constant (k) materials such as HfO2, HfSiO, Al2O3. An important transistor reliability issue is the threshold voltage stability under prolonged stressing. In this paper, we discuss two main causes of threshold voltage instability: charge trapping and negative bias temperature instability (NBTI) in high k gate dielectric stacks. Experimental and modeling studies for these threshold voltage instabilities are reviewed.

Band Edge Traps at Spectroscopically-Detected O-Atom Vacancies in Nanocrystalline ZrO2 and HfO2: An Engineering Solution for Elimination of O-Atom Vacancy Defects in Non-crystalline Ternary Silicate Alloys

Spectroscopic studies, supported by theory indicate that neutral and negatively charged O-atom vacancies are the most important intrinsic defects in nanocrystalline thin films of Hf (Zr)O2. O-atom vacancy defects are identified in this paper by different spectroscopic technique: vacuum ultra-violet spectroscopic ellipsometry, near edge x-ray absorption spectroscopy, and cathodo-luminescence spectroscopy. O-vacancy defects are active as i) interface traps for Si substrate injection of holes, and ii) bulk film traps for Si substrate injection of electrons. The markedly different electron and hole trapping properties are a potentially serious problem for threshold voltage control and stability in CMOS inverter FETs using nanocrystalline Hf(Zr)O2 dielectrics. O-vacancy defects are not observed specrtroscopically in thermally and chemically stable Zr Si oxynitride alloy films, (SiO2)x(Si3N4)y(ZrO2)z, that have been annealed at 1100ºC in Ar. Si3N4 concentrations in these alloys must be controlled within narrow limits, ~0.36 to 0.4, with equal SiO2 and ZrO2 concentrations of approximately 0.32 to 0.3.

Atomic Layer Deposited HfO2 and HfSiO to Enable CMOS Gate Dielectric Scaling, Mobility, and VTH Stability

Atomic layer deposited (ALD) Hf-based dielectrics have been studied to understand scaling, electron mobility, and threshold voltage stability issues in transistor devices. ALD HfO2 formed from TEMAHf and O3 was found to reach a scaling limit near Tphys=1.2 nm. Knowledge of this limit is important because mobility improvements are observed as HfO2 is scaled to 2.0 nm and below. Concurrent with mobility improvement, a reduction in transient charging is manifested as improved VTH and Id stability during constant voltage stress. HfO2 attributes include the following: EOT=1.0 nm, >100× Jg reduction vs. SiO2/PolySi, high field mobility of 82% universal SiO2 and ~20 mV of DVTH after 1000s stress at 1.8V. Similar results can be obtained for (HfO2)x(SiO2)1-x alloys. These results suggest that high-k dielectrics can be competitive with the current gate dielectric material SiON.

ZnO thin-film transistors with polycrystalline (Ba,Sr)TiO3 gate insulators

The electrical characteristics of ZnO thin-film transistors with high-k (Ba,Sr)TiO3 gate dielectrics are presented. The ZnO and (Ba,Sr)TiO3 thin films were deposited on Pt, exhibiting polycrystalline characteristics. The thin-film devices demonstrated transistor behavior over the range of 0–10V with a stable threshold voltage of approximately 1.2V. The field effect mobility, subthreshold slope, and on/off ratio were measured to be 2.3cm2V−1s−1, 0.25V∕decade, and 1.5×108, respectively. The measured transistor performance characteristics suggest that ZnO∕(Ba,Sr)TiO3 structures are well suited for both polycrystalline thin-film transistors for display applications and future higher performance transistors based on single crystal ZnO.

Temperature Dependence of Phase-Change Random Access Memory Cell

The temperature dependences of phase-change random access memory (PCRAM) cells on different Ge–Sb–Te phase-change recording materials are studied and compared. A Ge2Sb2Te5 phase-change film has a larger resistance margin and a higher thermal stability than Ge1Sb2Te4 and Ge1Sb4Te7 films. The set resistance, reset resistance, resistance margin and threshold voltage of PCRAM cells decrease with increasing temperature. A Ge2Sb2Te5 PCRAM cell has a higher thermal stability of threshold voltage than Ge1Sb2Te4 and Ge1Sb4Te7 PCRAM cells.

Backplane Requirements for Active Matrix Organic Light Emitting Diode Displays

AbstractOrganic light emitting diode (OLED) displays are a serious competitor to liquid crystal displays in view of their superior picture quality, higher contrast, faster on/off response, thinner profile, and high power efficiency. For large area and/or high-resolution applications, an active matrix OLED (AMOLED) addressing scheme is vital. The active matrix backplane can be made with amorphous silicon (a-Si), polysilicon, or organic technology, all of which suffer from threshold voltage shift and/or mismatch problems, causing temporal or spatial variations in the OLED brightness. In addition, the efficiency of the OLED itself degrades over time. Despite these shortcomings, there has been considerable progress in development of AMOLED displays using circuit solutions engineered to provide stable and uniform brightness. Indeed the design of AMOLED pixel circuits, particularly in low-mobility TFT technologies such as a-Si, is challenging due to the stringent requirements of timing, current matching, and low voltage operation. While circuit solutions are necessary, they are not sufficient. Process improvements to enhance TFT performance are becoming inevitable. This paper will review pertinent material requirements of AMOLED backplanes along with design considerations that address pixel architecture, contact resistance, and more importantly, the threshold voltage stability and associated gate overdrive voltage. In particular, we address the question of whether conventional PECVD can be deployed for high mobility and high stability TFTs, and if micro-/nano-crystalline silicon could provide the solution.

New Concepts for the Development of Active Functional Polymers for p and n-Type OFET- Applications

ABSTRACTHere we present a concept to improve the field effect transistor performance of P3HT in terms of threshold voltage stability as well as the stability in ambient atmosphere by introducing a strong acceptor dopant in the main polymer chain. In our concept the direct introduction of the acceptor dopant in the polymer main chain ensures the strucural stability against diffusion processes. P3HTs with different contents of acceptor molecules which are fixed linked in the main chain of the polymer , have been synthesized using the McCullough Grignard metathesis method. As acceptor unit has been integrated tetrafluorbenzene (TFB). The introduced dopant amount has been varied in order to obtain an optimum between the processability of the polymers and the resultant transistor performance.Compared to the p-type semionducting polymers the n-type organic materials are markedly less developed. Recently an interesting solution to this task has been proposed in the form of a conjugated ladder-type poly (benzo-bisimidazobenzo-phenanthroline) (BBL) showing either ambipolar or n-type field effect properties dependent upon the sample preparation and processing. However this rigid-chain ladder polymer is not soluble in the common organic solvents resulting in a rather complicated technological transfer. We report the significant improvement of the BBL-processing utilizing aqueous colloidal dispersions and their OFET-application. The resultant devices demonstrate ambipolar electronic transport with charge carrier mobilities in the range of 10−5 cm2/Vs without specific optimization procedures..

Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks

Over recent years, there has been increasing research and development efforts to replace SiO/sub 2/ with high dielectric constant (high-/spl kappa/) materials such as HfO/sub 2/, HfSiO, and Al/sub 2/O/sub 3/. An important transistor reliability issue is the threshold voltage stability under prolonged stressing. In these materials, threshold voltage is observed to shift with stressing time and conditions, thereby giving rise to threshold voltage instabilities. In this paper, we review various causes of threshold voltage instability: charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects in high-/spl kappa/ gate dielectric stacks. Experimental and modeling studies for these threshold voltage instabilities are reviewed.

BTI characteristics and mechanisms of metal gated HfO/sub 2/ films with enhanced interface/bulk process treatments

Significant deviations in BTI characteristics for metal gate HfO/sub 2/ films compared to silicon oxide based films prove that conventional reliability models based on SiO/sub 2/ films can no longer be directly applied to HfO/sub 2/ based MOSFETS. This study shows the use of conventional accelerated reliability testing in the Fowler-Nordheim tunneling regime to extrapolate time to failure at operating voltages (direct tunneling regime) overestimates device lifetimes. Additionally, unlike conventional gate oxides, the slope of /spl Delta/V/sub t/ versus time (or the rate of charge trapping) in HfO/sub 2/ MOSFETS is dependent on stress voltage. The HfO/sub 2/ based metal gated nMOSFETS show poor PBTI characteristics and do not meet the 10 year lifetime criterion for threshold voltage stability. On the other hand, HfO/sub 2/ based pMOSFETS show superior NBTI behavior and meet the 10 year lifetime criterion. These results are contrary to the observations with conventional gate dielectrics. This paper explores the anomalous charge trapping behavior and provides a comprehensive study of the PBTI characteristics and recovery mechanisms in metal gated HfO/sub 2/ films.

Stability of fully deuterated amorphous silicon thin-film transistors

The threshold voltage stability of fully deuterated (a-Si:D) and hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) is compared. The difference in the kinetic energy of D+ and H+ ions upon impact with the growing surface during radio-frequency plasma-enhanced chemical vapor deposition leads to material having different physical properties for the same nominal deposition conditions. However, a-Si:D and a-Si:H grown at the same growth rate by adjusting the gas pressure have almost identical properties. By using the growth rate as a normalizing parameter for comparing a-Si:H and a-Si:D TFTs, it is shown that there is no difference in the stability of a-Si:D compared with a-Si:H TFTs. This study rules out the possibility of a giant isotopic effect in amorphous silicon TFTs, and supports the model for Si dangling bond defect creation in a-Si:H where the breaking of weak Si–Si bonds is the rate-limiting step.

Annealing temperature stability of Ir and Ni-based Ohmic contacts on AlGaN∕GaN high electron mobility transistors

Ti ∕ Al ∕ Ir ∕ Au Ohmic contacts on AlGaN∕GaN high electron mobility transistors (HEMTs) show promising electrical performance, with lower specific contact resistance than obtained with the more conventional Ti∕Al∕Ni∕Au metallization. HEMTs with both types of metallization have been measured up to 550°C. We find that the dc performance of devices with Ir-based contacts is significantly better at each temperature up to this maximum value, with higher transconductance (gm), saturated drain-source current (IDSS), and more stable threshold voltage (Vth). These contacts look very promising for HEMT power amplifier applications involving high temperature operation.

Stable threshold voltage extraction using Tikhonov's regularization theory

We propose a new threshold voltage extraction with stability based on Tikhonov's regularization theory. It suppresses the instability of the transconductance change method and gives mathematically exact solution. Following the mathematical derivation, we convert the procedure into the MATLAB programming for users' convenience. Finally, the proposed method extracts the threshold voltage close to the physically meaningful one which means the gate-to-source voltage where /spl phi//sub s/=2/spl phi//sub f/+V/sub SB/. To confirm the proposed one, we compare it with others such as the linear extraction and the normalized mutual integral difference method. It was found that the proposed one extracted the physically meaningful threshold voltage very closely. Moreover, it is also observed that there is a high correlation between the proposed and the normalized mutual integral difference method.

Schottky emitter using boron-doped diamond

In this article, a microboron-doped diamond Schottky emitter for microelectron sources is presented. We fabricated an emitter tip on the top of the cantilever-type heating element using selective diamond deposition and silicon molding techniques. The fabricated diamond emitter shows high brightness emission current of 800 nA at a tip-anode (screen) electric field of 0.55 V/μm and tip heating voltage of 25 V. From the estimation using the Schottky emission model, the temperature of the emitter was found out 862±10 °C. The long-term stability of the emission current was characterized. This kind of structure can be utilized for electron sources with potential advantages of low threshold voltage and long lifetime stability in the proper emission condition.

Boron segregation and electrical properties in polycrystalline Si1−x−yGexCy and Si1−yCy alloys

In this article, we report strong boron segregation to polycrystalline Si1−x−yGexCy from polysilicon during thermal anneals in the temperature range of 800–900 °C. This effect is larger than previous reports of segregation to single-crystal Si1−xGex and increases with carbon concentration. Segregation also occurs in polycrystalline Si1−yCy, revealing that carbon by itself can drive the segregation (without germanium present). This segregation is used to model the enhanced threshold voltage stability of p-channel metal oxide semiconductor field effect transistors with boron-doped polycrystalline Si1−x−yGexCy gates. We also study the electrical properties of polycrystalline Si1−x−yGexCy. For low carbon concentrations (0.4%), polycrystalline Si1−x−yGexCy has a similar level of dopant activation and mobility as polycrystalline Si1−xGex; increasing the concentration to 1.6% results in significant losses in both. Annealing the films for time scales similar to those needed for segregation causes no degradation of the electrical properties, indicating that electrically inactive defects are not driving the segregation.

Drain-Bias Dependence of Threshold Voltage Stability of Amorphous Silicon TFTs

Amorphous silicon (a-Si:H) thin-film transistors (TFTs) used in emerging, nonswitch applications such as analog amplifiers or active loads, often have a bias at the drain terminal in addition to the gate that can alter their threshold voltage (V/sub T/) stability performance. At small gate stress voltages (0/spl les/V/sub ST//spl les/15 V) where the defect state creation instability mechanism is dominant, the presence of a bias at the TFT drain decreases the overall shift in V/sub T/(/spl Delta/V/sub T/) compared to the /spl Delta/V/sub T/ in the absence of a drain bias. The measured shift in V/sub T/ appears to agree with the defect pool model that the /spl Delta/V/sub T/ is proportional to the number of induced carriers in the a-Si:H channel.

Effects of deuterium anneal on MOSFETs with HfO2 gate dielectrics

The effects of high-temperature (600/spl deg/C) anneal in a dilute deuterium (N/sub 2/ : D/sub 2/= 96 : 4) atmosphere was first investigated and evaluated in comparison to high-temperature forming gas (N/sub 2/ : H/sub 2/= 96 : 4) anneal (600/spl deg/C) and nonanneal samples. The high-temperature deuterium anneal was as effective as the forming gas anneal in improving MOSCAP and MOSFET characteristics such as the C-V curve, drain current, subthreshold swing, and carrier mobility. These can be attributed to the improved interface quality by D/sub 2/ atoms. However, unlike the forming gas anneal, the deuterium anneal provided the hafnium oxide (HfO/sub 2/) gate dielectric MOSFET with better reliability characteristics such as threshold voltage (V/sub T/) stability under high voltage stress.

Threshold Voltage Performance of a-Si:H TFTs for Analog Applications

AbstractAmorphous silicon (a-Si:H) thin-film transistors (TFT) used in emerging, non-switch applications such as analog amplifiers or active loads, often have a bias at the drain terminal in addition to the gate that can alter their threshold voltage (VT) stability performance. At small gate voltages (0 ≤ VST ≤ 15 V) where the defect state creation instability mechanism is dominant, the presence of a bias at the TFT drain is found to decrease the shift in VT (ΔVT) compared to the ΔVT in the absence of a drain bias. In this paper, a ΔVT model accounting for TFT drain bias, is used to predict the performance of a-Si:H analog circuits in active pixel sensor (APS) medical xray imaging and active matrix, organic light emitting diode (AMOLED) display applications.