Evolution of Interface State Density and Near Interface Oxide Traps under Controlled Nitric Oxide Annealing in SiO<sub>2</sub>/SiC Lateral MOSFETs

Abstract

In this paper, the effect of different post oxide deposition nitridation processes in NO on n-channel lateral MOSFETs fabricated on implanted 4H-SiC were investigated. In particular, the electrical behavior of the MOSFETs was deeply investigated not only in terms of SiO2/SiC interface state density and field effect mobility, but also considering the threshold voltage stability effect. The aim of this work was to explore to which extent post oxide deposition annealing in NO is beneficial for the MOS interface behavior and when their detrimental effects start to become predominant on the device performances. Here, the separation of the trapping states at the interface – either close to the conduction and valence band edges – and the near interface oxide traps are reported for the different duration of the post oxide deposition annealing. In fact, cyclic gate bias stress was employed in order to analyze the behavior of the trapping states and to correlate them with the variation of the benefits in terms of the channel mobility (that saturates at about 80 cm2V-1s-1), and on the threshold voltage instability effect. In particular, prolonged PDAs may induce an increase of the amount of trapping states close to the valence band edge and inside the insulator of about 20% and 50 %, respectively.