SRAM Design Research Articles

Novel tri-independent-gate FinFET for multi-current modes control

In this paper, a novel tri-independent-gate (TIG) FinFET is presented for multi-current modes control for the first time. The entire integration flow of proposed TIG FinFET is fully compatible with the mainstream gate-first HKMG FinFET process. Five kinds of ON state modes and threshold voltages can be offered by TIG FinFET without additional voltage sources, and it is demonstrated to have a great potential in dynamic voltage SRAM design. The critical electrical parameters of TIG FinFET in different modes are fully investigated with TCAD simulation and compared to the traditional FinFET. TIG FinFET with double fins is found to possess a distinct different output and capacitance characteristics with single fin FinFET. The underlying physical mechanisms are analyzed and investigated in detail.

Monolayer Transistor SRAMs

Monolayer heterojunction FETs based on vertical heterogeneous transition metal dichalcogenides (TMDCFETs) and planar black phosphorus FETs (BPFETs) have demonstrated excellent subthreshold swing, high I ON I OFF , and high scalability, making them attractive candidates for post-CMOS memory design. This article explores TMDCFET and BPFET SRAM design by combining atomistic self-consistent device modeling with SRAM circuit design and simulation. We perform detailed evaluations of the TMDCFET/BPFET SRAMs at a single bitcell and at SRAM array level. Our simulations show that at low operating voltages, TMDCFET/BPFET SRAMs exhibit significant advantages in static power, dynamic read/write noise margin, and read/write delay over nominal 16nm CMOS SRAMs at both bitcell and array-level implementations. We also analyze the effect of process variations on the performance of TMDCFET/BPFET SRAMs. Our simulations demonstrate that TMDCFET/BPFET SRAMs exhibit high tolerance to process variations, which is desirable for low operating voltages.

Comparative Analysis of 6T, 7T, 8T, 9T, and 10T Realistic CNTFET Based SRAM

CMOS technology below 10 nm faces fundamental limits which restricts its applicability for future electronic application mainly in terms of size, power consumption, and speed. In digital electronics, memory components play a very significant role. SRAM, due to its unique ability to retain data, is one of the most popular memory elements used in most of the digital devices. With aggressive technology scaling, the design of SRAM is seriously challenged in terms of delay, noise margin, and stability. This paper compares the performance of various CNTFET based SRAM cell topologies like 6T, 7T, 8T, 9T, and 10T cell with respect to static noise margin (SNM), write margin (WM), read delay, and power consumption. To consider the nonidealities of CNTFET, variations in tube diameter and effect of metallic tubes are considered for various structures with respect to various performance metrics like SNM, WM, read delay, and power consumption.

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.

Trade-off for Leakage Power Reduction in Deep Sub Micron SRAM Design

Present day electronic industry faces the major problem of standby leakage current, as the processor speed increases, there is requirement of high speed cache memory. SRAM being mainly used for cache memory design, several low power techniques are being used for SRAM cell design. Full CMOS 6T SRAM cell is the most preferred choice for digital circuits. This paper reviews various leakage power techniques used in 6T SRAM cell and their comparative study.

A novel design of low power and high read stability Ternary SRAM (T-SRAM), memory based on the modified Gate Diffusion Input (m-GDI) method in nanotechnology

The conventional complementary metal-oxide semiconductor (CMOS) design techniques confront to the limitation of designing the integrated circuits (ICs), especially memories, with multiple-valued logic (MVL) in nanotechnology. Gate diffusion input (GDI) technique, provides the possibility to design low power logic gates with small chip area and interconnection capacitors while the number of transistors is diminished. In this paper first ternary GDI (t-GDI) cell based on the proposed binary (two-valued) modified GDI (m-GDI) method, which is appropriate for designing circuits using MVL, is designed. Then, by using the standard ternary inverter (STI) gate implemented based on the proposed t-GDI cell with better noise margins and also small standard deviation of results, first novel design of a ternary SRAM (T-SRAM) cell is presented for nano process, which has smaller standby power dissipation and standard deviation for delay of writing and reading cycles, better read static noise margin (RSNM) and lower signal control complexity. The design of specific structure of 4-words×4-bits, ternary SRAM (4×4 T-SRAM) shows that the number of connections, chip area is decreased and power-delay product (PDP) criterion is improved for writing and reading cycles with significant small standard deviation in compare with the other similar T-SRAMs designed.The effects of different process variations such as density, number of CNTs and temperature variations are extensively evaluated by Monte-Carlo simulation, with respect to performance metrics such as delay, power dissipation and PDP of writing and reading cycles, also RSNM parameter for SRAM cells. The comparison exhibits that in all cases the proposed T-SRAM cell showing a substantial small standard deviation and considerable lower variability percentage than state-of-the art SRAM cells. So, the proposed T-SRAM cell design has the lowest sensitivity variations, thus it is an attractive choice for nano technology application in the presence of impact process and temperature variations. The simulation is done with Synopsys H-SPICE simulator in 32nm technology under the condition of variations.

Design and Analysis of Transient Fault Tolerance in SRAM with different NT Techniques

In digital domain applications one of the main important analyses is to check the system performance even if the fault is occurred. This paper describes the fault tolerance technique based on the software approach for SRAM memory unit present in the multi core system using Processor Level Redundancy (PLR). The PLR proceeds with software-centric approach, soft fault tolerance which ensuring a correct software execution. In this approach we applied here only for SRAM available in the processor. This scheme is used at user space level which does not necessitate changes to the original application. In this approach is used to detect the soft errors presented in the memory unit and it will recover from the fault without stop the process of the memory unit. To design the SRAM here we use the different nT technique. The main goal of this approach is which implements fault error detection and fault recovery mechanism to check the performance of the memory unit. This paper presents software based nT for SRAM design and analysis transient fault tolerance using Process Level Redundancy (PLR) is lower when comparable to existed.

Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC

The breakdown of Dennard scaling prevents us from powering all transistors simultaneously, leaving a large fraction of dark silicon. This crisis has led to innovative work on power-efficient core and memory architecture designs. However, the research for addressing dark silicon challenges with network-on-chip (NoC), which is a major contributor to the total chip power consumption, is largely unexplored. In this paper, we comprehensively examine the network power consumers and the drawbacks of the conventional power-gating techniques. To overcome the dark silicon issue from the NoC's perspective, we propose DimNoC, a dim silicon scheme, which leverages recent drowsy SRAM design and spin-transfer torque RAM (STT-RAM) technology to replace pure SRAM-based NoC buffers. In particular, we propose two novel hybrid buffer architectures: 1) a hierarchical buffer architecture, which divides the input buffers into a set of levels with different power states and 2) a banked buffer architecture, which organizes the drowsy SRAM and the STT-RAM in different banks, and accesses them in an interleaved fashion to hide the long write latency of STT-RAM. In addition, our hybrid buffer design enables NoC data retention mechanism by storing packets in drowsy SRAM and nonvolatile STT-RAM in a lossless manner. Combined with flow control schemes, the NoC data retention mechanism can improve network performance and power simultaneously. Our experiments over real workloads show that DimNoC can achieve 30.9% network energy saving, 20.3% energy-delay product reduction, and 7.6% router area reduction compared with pure SRAM-based NoC design.

Power efficient SRAM design with integrated bit line charge pump

Bit line toggling of SRAM systems in write operations leads to the largest portion of power dissipation. To reduce this amount of power loss and achieve power efficient memory, we propose a new SRAM design that integrates charge pump circuits to harvest and reuse bit line charge. In this work, a power-efficient charge recycling SRAM is designed and implemented in 180nm CMOS technology. Post-layout simulation demonstrates an 11% of power saving and 3.8% of area overhead, if the bit width of SRAM is chosen as 8. Alternatively, 22% of power reduction is obtained if the bit width of SRAM is extended to 64. Compared with existing charge recycling SRAM schemes, this proposed SRAM is robust to process variation, demonstrates good read/write stability, and illustrates better trade-off between design complexity and power reduction.

Design and Optimization of 6T FinFET SRAM in 45 nm Technology

Design and Optimization of 6T FinFET SRAM in 45 nm Technology

A Charge-Recycling Assist Technique for Reliable and Low Power SRAM Design

This paper presents a novel charge-recycling SRAM assist circuit to reduce the dynamic power consumption of SRAM assist technique. By collaboratively combining the read and write assist schemes, the wasted charge in conventional read assist circuit can be efficiently recycled in write assist technique. In order to compare the dynamic power consumption at ISO minimum operating voltage $({V}_{\mathrm{MIN}})$ condition, the most probable failure point (MPFP) simulations are performed using 14 nm FinFET technology model. Compared to the conventional assist schemes, thanks to the charge-recycling, 41% power saving, and 2.3% area reduction can be achieved by using the proposed SRAM assist circuit.

Device-Circuit Cosimulation for Energy Efficiency in Sub-10-nm Gate Length Logic and Memory

Sub-10-nm gate length devices are expected to have severe short channel effects along with new leakage mechanisms, such as direct source-to-drain tunneling (DSDT). In this paper, in order to improve the leakage and to obtain the highest performance/stability in such deeply scaled devices, we perform device–circuit cosimulation for sub-10-nm gate length to optimize devices for logic and memory. For that purpose, double-gate MOSFETs with sub-10-nm gate length are optimized using symmetric/asymmetric gate-to-source/drain underlaps to improve the ON-state current to the OFF-state current ratio and the intrinsic gate delay. Using resulting device characteristics, the effectiveness of supply gating to improve standby leakage in the circuits is studied. We show that supply gating is effective in reducing DSDT current, as well as thermionic leakage current. Also, various SRAM designs are explored to improve stability and leakage in sub-10-nm gate length bit-cells. The analysis shows that 6T SRAM bit-cells with asymmetrically underlapped devices can provide improvement in read stability over symmetric 6T bit-cells, as well as traditional 6T bit-cells. However, the need for higher stability in the sub-10-nm gate length regime due to parameter variation would require us to investigate other bit-cell configurations. Our analysis on 1R/1W differential 8T SRAM bit-cells show that significant increase in read/write stability as well as improvement in write time, and leakage can be achieved compared with the optimized 6T SRAM bit-cells.

DESIGN OF A 4-BIT NON-VOLATILE SRAM USING MAGNETIC TUNNEL JUNCTION

In this paper, we propose a non-volatile SRAM, which presents simultaneously low power dissipation and high speed. This SRAM is based on MRAM (Magnetic RAM technology on standard CMOS. In this non-volatile SRAM design, we use Magnetic Tunnel Junctions (MTJ) as storage element. A 4-bit SRAM cell is designed and its read-write operations are described. Sense Amplifier is used in the read operation model. Two Write-Enable transistors and two inverters are used in the write operation model. The 4-bit SRAM cell has been implemented using Tanner tool. The operation of the SRAM cell is clearly understood from the output waveforms obtained after implementation. The structure and working of Magnetic Tunnel Junction is studied. The design of a Non-Volatile SRAM using Magnetic Tunnel Junction is proposed.

Asymmetric Underlapped Sub-10-nm n-FinFETs for High-Speed and Low-Leakage 6T SRAMs

A 6T SRAM design at a sub-10-nm node calls for carefully designed transistors so that new leakage mechanisms, such as direct source-to-drain tunneling (DSDT) and short channel effects that lead to $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ degradation, are kept under control. In this paper, we explore asymmetric underlap for mitigating DSDT, thermionic leakage, and for improving $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ of double-gate FinFETs. We demonstrate that for 6T SRAMs, asymmetric underlapped n-FinFETs are superior to symmetric underlap/overlap in improving access time and leakage power. We model the atomistic nature of sub-10-nm FinFET channels, quantum confinement, subband nonparabolicity, and anisotropy latent at such length scales using quantum physics-based simulators instead of the conventional semiclassical, drift-diffusion-based Technology Computer Aided Design tools. Using a device/circuit/system-level codesign approach consisting of NEMO5 quantum mechanical device simulations, HSPICE circuit simulations of a 6T SRAM bit cell, and a system-level analysis of a 8-kB L1 and 4-MB L2 cache, we show that the adoption of optimized asymmetric underlapped n-FinFETs can offer up to 6.5% improvement in L1 cache access times and a 2.3-mW reduction in L2 cache leakage power, while delivering noise margins close to symmetric underlapped n-FinFET-based caches.

Parameter Analysis of different SRAM Cell Topologies and Design of 10T SRAM Cell at 45nm Technology with Improved Read Speed

Parameter Analysis of different SRAM Cell Topologies and Design of 10T SRAM Cell at 45nm Technology with Improved Read Speed

SRAM Cell Memory Design for Power Reduction using Low Power Techniques

SRAM memory cell consists of many input signals like precharge, write enable, sense amplifier enable, read enable and row and column encoders. To develop a novel SRAM design, different transistor circuits are available. Normally SRAM cell uses conventional 4 transistor circuit in low power applications. In this thesis, instead of conventional circuit, 8 transistor (8T) and ten transistor(10T) designs are tried to improve the power efficiency under various temperature conditions. Initially 8T and 10T SRAM circuits are designed with write driver logic and the power is calculated for both static and dynamic conditions. Then, charge recycling logic is tried along with precharge logic with various temperature ranges. From the design, total power, static power, dynamic power, Transient time, transient delay and static current in 8T SRAM and 10T SRAM cell are calculated and compared. The 8T SRAM has the least transistor count and least area efficient, but speed of operation is somewhat reduced. Further, increase in the transistor count in 10T SRAM cell, however, makes area and delay large in room temperature. When temperature increases from a particular value, the 10T SRAM cell performs better than the 8T SRAM cell. This justifies the use of 10T SRAM cell for low power applications with varying temperature conditions. The proposed SRAM memory design can be implemented in any digital circuit.

CMOS Buffer Design Approach for Low Power and Lower Delay SRAM Design

Leakage power dissipation of on-chip SRAM constitutes a significant amount of the total chip power consumption in microprocessors and System on chips. With technology scaling, it is becoming increasingly challenging to maintain the yield while attempting to reduce the leakage power of SRAMs. The sources of SRAM power are the sum of the power consumed by decoders, memory array, write drivers, Sense amplifiers, and I/O line drivers. This paper is mainly focuses on the development of power and delay efficient SRAM structure. The paper describes the comparison of different CMOS tapper buffer topology's as word line drivers while driving large capacitive loads for minimizing power dissipation and propagation delay. The comparison has been designed and simulated using Cadence Virtuoso Spectre in 180nm technology.

Low Store Power, High Speed, High Density, Nonvolatile SRAM Design with Spin Hall Effect-Driven Magnetic Tunnel Junctions

As static power caused by leakage currents has become a critical challenge for the CMOS technology power-gating techniques, which employ nonvolatile data retention circuits, e.g., nonvolatile static random-access memory (NV-SRAM) are expected to efficiently solve this challenge. One of the key features of NV-SRAM is to utilize nonvolatile devices, such as resistive RAM, phase change memory, and magnetic tunnel junction (MTJ), to store the runtime data when system is in the standby power-off state. Among them, MTJ-based NV-SRAM is widely considered as the most potential candidate in high-speed, low-power, and high-reliability applications, thanks to the advantageous features of the MTJ devices, such as fast data store/restore operation, low critical writing current density, and high endurance. In this paper, we propose a novel NV-SRAM design with spin Hall effect (SHE)-driven MTJ devices. In specific, two embodiments are designed based on the magnetic anisotropy property (i.e., in-plane or perpendicular) of the MTJ device. Using our previously developed SHE-MTJ model and a CMOS design kit, circuit operation and performance of the proposed NV-SRAM designs were demonstrated at the 40-nm technology node. Simulation results show that our proposed NV-SRAM design achieves performance improvement in terms of power, delay, and area, compared with conventional designs.

Low power SRAM design for 14 nm GAA Si-nanowire technology

This paper presents a low power and stable 6-T nanowire SRAM cell design by tuning the extension length of the access transistor. Our approach significantly reduces the power dissipation with a low active area and improves the SRAM cell read stability. We utilize device design parameters such as the nanowire diameter, the number of nanowires, and the device extension length to improve the stability of the SRAM cells. We find that the extension length tuning technique exhibits 15% and ~60% savings in active area and static power consumption, respectively, in comparison to a conventional multi-nanowire tuning technique. In addition, the proposed technique achieves 6% and 8% improvements in the read and hold noise margins, respectively, with a 6.5% decrease in write noise margin and a ~14% increase in the read/write access time. Our results show that the extension length-tuned access transistor is an excellent option for improving the satiability with low power for sub-14-nm technologies.

An Efficient Error Detection Technique for 3D Bit-Partitioned SRAM Devices

As the feature sizes and the operating charges continue to be scaled down, multi-bit soft errors are becoming more critical in SRAM designs of a few nanometers. In this paper, we propose an efficient error detection technique to reduce the size of parity bits by applying a 2D bit-interleaving technique to 3D bit-partitioned SRAM devices. Our proposed bit-interleaving technique uses only 1/K (where K is the number of dies) parity bits, compared with conventional bit-interleaving structures. Our simulation results show that 1/K parity bits are needed with only a 0.024-0.036% detection error increased over that of the existing bit-interleaving method. It is also possible for our technique to improve the burst error coverage, by adding more parity bits.