Spin-transfer Torque Random Access Memory Research Articles

Quantifying External Magnetic Field Immunity of the Write Process in Perpendicular Spin-Transfer-Torque Random Access Memory

The resilience of write operation in spin-transfer-torque random access memory (STT-RAM) under external magnetic field disturbances is often overlooked. In this work, write error rates (WER) of STT-RAM are calculated, including the effects of magnetic field perturbation of varying magnitude and direction. WER is calculated directly from the numerical solution of the two-dimensional Fokker-Planck equation that enables the estimation of ultra-low probability tails of WER. The results show orders of magnitude increase in WER when an external magnetic field is applied along a direction non-collinear with the easy axis of the magnet. Numerical results are explained quantitatively from an analytical theory that confirms the appearance of additional zero-torque “stagnation points” on the unit sphere’s surface, representing the magnetization vector of constant magnitude. Simulated bit error rates are calculated under varying applied current and write pulse duration. Implications on the active write mode magnetic immunity are discussed. The results present critical insights into the switching process of perpendicular STT-RAM memory cells exposed to external magnetic field perturbation and call for a thorough characterization of such failure modes for quantifying external magnetic field tolerance.

Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array

Embedded memories were once utilized to transfer information between the CPU and the main memory. The cache storage in most traditional computers was static-random-access-memory (SRAM). Other memory technologies, such as embedded dynamic random-access memory (eDRAM) and spin-transfer-torque random-access memory (STT-RAM), have also been used to store cache data. The SRAM, on the other hand, has a low density and severe leakage issues, and the STT-RAM has high latency and energy consumption when writing. The gain-cell eDRAM (GC-eDRAM), which has a higher density, lower leakage, logic compatibility, and is appropriate for two-port operations, is an attractive option. To speed up data retrieval from the main memory, future processors will require larger and faster-embedded memories. Area overhead, power overhead, and speed performance are all issues with the existing architecture. A unique mixed-V T 3T GC-eDRAM architecture is suggested in this paper to improve data retention times (DRT) and performance for better energy efficiency in embedded memories. The GC-eDRAM is simulated using a standard complementary-metal-oxide-semiconductor (CMOS) with a 130nm technology node transistor. The performance of a 2kbit mixed-VT 3T GC-eDRAM array were evaluated through corner process simulations. Each memory block is designed and simulated using Mentor Graphics Software. The array, which is based on the suggested bit-cell, has been successfully operated at 400MHz under a 1V supply and takes up almost 60-75% less space than 6T SRAM using the same technology. When compared to the existing 6T and 4T ULP SRAMs(others' work in K. Sharma et al.and A. Goyal et al.)the retention power of the proposed GC-eDRAM is around 80-90% lower.

Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches

STT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based on-chip caches. Due to its high density and low leakage power, STT-RAM can be used to build massive capacity last-level caches (LLC). Unfortunately, STT-RAM has a much longer write latency and a much greater write energy than SRAM. Researchers developed hybrid caches made up of SRAM and STT-RAM regions to cope with these challenges. In order to store as many write-intensive blocks in the SRAM region as possible in hybrid caches, an intelligent block placement policy is essential. This paper proposes an adaptive block placement framework for hybrid caches that incorporates metadata embedding (ADAM). When a cache block is evicted from the LLC, ADAM embeds metadata (i.e., write intensity) into the block. Metadata embedded in the cache block are then extracted and used to determine the block’s write intensity when it is fetched from main memory. Our research demonstrates that ADAM can enhance performance by 26% (on average) when compared to a baseline block placement scheme.

EXTENT: Enabling Approximation-Oriented Energy Efficient STT-RAM Write Circuit

Spin Transfer Torque Random Access Memory (STT-RAM) has garnered interest due to its various characteristics such as non-volatility, low leakage power, high density. Its magnetic properties have a vital role in STT switching operations through thermal effectiveness. A key challenge for STT-RAM in industrial adaption is the high write energy and latency. In this paper, we overcome this challenge by exploiting the stochastic switching of STT-RAM cells and, in tandem, with circuit-level approximation. We enforce the robustness of our technique by analyzing the vulnerability of write operation against radiation-induced soft errors and applying a low-cost improvement. Due to serious reliability challenges in nanometer-scale technology, the robustness of the proposed circuit is also analyzed in the presence of CMOS and magnetic tunnel junction (MTJ) process variation. Compared to the state-of-the-art, we achieve 33.04% and 5.47% lower STT-RAM write energy and latency, respectively, with a 3.7% area overhead, for memory-centric applications.

Optoelectronic Readout of STT-RAM Based on Plasmon Drag Effect

An opto-electronic readout of the memory state in spin transfer torque random access memory (STT-RAM) cells is proposed. A single optical beam illuminating an array of STT-RAM cells creates electrical potential along each STT-RAM cell due to optical rectification that can be further enhanced through plasmon drag effect (PLDE). Then, the photo-induced voltage is assumed to be measured by conventional electronics. Here, a theoretical modeling is performed, where the results provide an estimate of the photo-induced voltage in each memory cell and its variation with respect to the changes in state of the memory cell (parallel vs anti-parallel). Our study shows that the plasmonic enhancement facilitates ${\sim }$ 20 times enhancement in the voltage change due to state change of the each memory cell, compared to the case of out-of-resonance excitation. This enhancement potentially improves the memory readout rate if a proper supporting electronic circuit is available.

Self-Referenced Single-Ended Resistance Monitoring Write Termination Scheme for STT-RAM Write Energy Reduction

Essential design requirements for a sense amplifier (SA) used in the resistance monitoring write termination (RM-WT) scheme are suggested to reduce the write energy of spin-transfer-torque random access memory (STT-RAM) while achieving a write pass yield comparable to that of a conventional write operation. In addition, a self-referenced single-ended RM-WT (SS-RM-WT) scheme is proposed. To reduce the offset voltage, a single-ended sensing circuit (SE-SC) is used in the SA. A data-aware input voltage-transfer method is also adopted in the SE-SC to maximize the input voltage difference. By adopting a capacitor between the output of the SE-SC and the input of an inverter generating a logical output used for the write termination, the conflict between maintaining and changing the output of the SE-SC is resolved. The simulation results using the industry-compatible 65-nm technology HSPICE model parameters show that the proposed SS-RM-WT scheme achieves a 44% write energy saving on average without increasing the write error rate. Area overhead is only 11.8% for a 256-kb STT-RAM array, whereas that of the previous self-referenced RM-WT schemes is up to 42.5%.

Machine Learning for Statistical Modeling

We propose a methodology to perform process variation-aware device and circuit design using fully physics-based simulations within limited computational resources, without developing a compact model. Machine learning (ML), specifically a support vector regression (SVR) model, has been used. The SVR model has been trained using a dataset of devices simulated a priori, and the accuracy of prediction by the trained SVR model has been demonstrated. To produce a switching time distribution from the trained ML model, we only had to generate the dataset to train and validate the model, which needed ∼500 hours of computation. On the other hand, if 10 6 samples were to be simulated using the same computation resources to generate a switching time distribution from micromagnetic simulations, it would have taken ∼250 days. Spin-transfer-torque random access memory (STTRAM) has been used to demonstrate the method. However, different physical systems may be considered, different ML models can be used for different physical systems and/or different device parameter sets, and similar ends could be achieved by training the ML model using measured device data.

Study on Energy Reduction Techniques in STT-RAM

Spin Transfer Torque Random Access Memory (STT-RAM) is suitable to be considered for cosmic memory. In STT-RAM the altercative period of attractive burrowing intersection is exchanged by the showing up of turn enraptured current over the intersection and it appear to be the most preparing elective with the more thickness and low introduction power, one of the major test for STT-RAM is the more write current, this paper proposes dual source write assist circuit method to reduce the equal compose vitality that prompts a diminishing in power utilization and the limit voltage of dynamic transistor to rising temperature. The MTJ temperature will increase than the write error rate is reduced. The final result is by effective use of VDD and threshold voltage values the write energy will be reduced. Right now, results utilizing a CMOS 65-nm get to transistor and the 40-nm MTJ innovation affirm that the projected compose help strategy prompts 81% of robustness is spared and its further incorporates just 9.6% territory excess to a 16-kb of STT-RAM cluster. And furthermore, another compose help technique is proposed to the end the compose activity in the wake of exchanging happens in the attractive burrowing intersection (MTJ), thus the both compose time vitality utilization of 1T-1MTJ piece cells will create.

Adaptive MRAM Write and Read with MTJ Variation Monitor

Temperature and wafer-level process variations significantly degrade operation efficiency of Spin-transfer torque random access memory (STT-MRAM) and magnetoelectric random access memory (MeRAM), where the write and read reliability issues are exacerbated by the variations. We propose adaptive write and read schemes for highly efficient STT-MRAM and MeRAM programming and sensing that optimally selects write and read pulses to overcome process and temperature variation. With adaptive write, the write latency of STT-MRAM and MeRAM cache are reduced by up to 17 and 59 percent respectively, and application run time is improved by up to 41 percent. With adaptive read, the sensing margin is dramatically improved by 1.4X while maintaining read disturbance correctable by error-correcting-code (ECC) correction. To further mitigate read disturbance impact on memory system, additional adaptive read scheme can dynamically lower read voltage according to the proposed monitor result. It can extend memory service time by haft to one year, and reduce read disturbance induced memory failure by 59 to 84 percent. To better support these schemes, we also propose, design, and evaluate low-cost MTJ-based variation monitor, which precisely senses process and temperature variation. The monitor is over 10X faster, 5X more energy-efficient, and 20X smaller compared with conventional thermal monitors of similar accuracy.

Challenges and Applications of Emerging Nonvolatile Memory Devices

Emerging nonvolatile memory (eNVM) devices are pushing the limits of emerging applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Among several alternatives, phase change memory, spin-transfer torque random access memory, and resistive random-access memory (RRAM) are major emerging technologies. This review explains all varieties of prototype and eNVM devices, their challenges, and their applications. A performance comparison shows that it is difficult to achieve a “universal memory” which can fulfill all requirements. Compared to other emerging alternative devices, RRAM technology is showing promise with its highly scalable, cost-effective, simple two-terminal structure, low-voltage and ultra-low-power operation capabilities, high-speed switching with high-endurance, long retention, and the possibility of three-dimensional integration for high-density applications. More precisely, this review explains the journey and device engineering of RRAM with various architectures. The challenges in different prototype and eNVM devices is disused with the conventional and novel application areas. Compare to other technologies, RRAM is the most promising approach which can be applicable as high-density memory, storage class memory, neuromorphic computing, and also in hardware security. In the post-CMOS era, a more efficient, intelligent, and secure computing system is possible to design with the help of eNVM devices.

Enhancing Reliability of Emerging Memory Technology for Machine Learning Accelerators

An efficient and reliable Multi-Level Cell (MLC) Spin-Transfer Torque Random Access Memory (STT-RAM) is proposed based on a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><u>D</u>rop-<u>A</u>nd-<u>R</u>earrange <u>A</u>pproach</i> , called <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DARA</i> . Since CNN models are rather robust, less important bits are dropped, allowing important bits to be written in safe and reliable Single-Level Cell mode. Also, bits are <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rearranged</i> to make the representation better aligned with memory cell characteristics. Bits with higher impact on the features value are stored in safer bit positions reducing the chance of read/write circuits to malfunction. Experimental results show that our approach provides comparable to error-free scenario reliability level, while doubling the bandwidth and maintaining error rate of less than 0.02 percent.

Reduction of the switching current in perpendicularly magnetized nanomagnets using an antiferromagnetic coupling structure

This paper reports a current-induced magnetization switching with a nanosecond-scale pulse current in a nanomagnet using a perpendicularly magnetized synthetic antiferromagnetic coupling (p-AFC) structure. The results indicate that the magnetization switching current in the p-AFC structure is less than that in the single-nanomagnet structure with perpendicular anisotropy when the differences in thickness and saturation magnetization between the upper and lower layers of the p-AFC structure are small and the Gilbert damping constant is also small. The results also show that the p-AFC structure can reduce the switching current when the pulse duration is short and its structure is effective for a high-speed switching. The results of this study shall be useful in the design of spin-transfer torque random access memory.

Integer linear programming model for allocation and migration of data blocks in the STT‐RAM‐based hybrid caches

Spin-transfer torque random access memory (STT-RAM) has emerged as an eminent choice for the larger on-chip caches due to high density, low static power consumption and scalability. However, this technology suffers from long latency and high energy consumption during a write operation. Hybrid caches alleviate these problems by incorporating a write-friendly memory technology such as static random access memory along with STT-RAM technology. The proper allocation of data blocks has a significant effect on both performance and energy consumption in the hybrid cache. In this study, the allocation and migration problem of data blocks in the hybrid cache is examined and then modelled using integer linear programming (ILP) formulations. The authors propose an ILP model with three different objective functions which include minimising access latency, minimising energy and minimising energy-delay product in the hybrid cache. Evaluations confirm that the proposed ILP model obtains better results in terms of energy consumption and performance compared to the existing hybrid cache architecture.

Array of symmetric nanohole dimers with high sensitivity for detection of changes in an STT-RAM ultrathin dielectric layer

A dimer nanohole array is proposed for in situ characterization of radiation damages in spin transfer torque random access memory (STT-RAM) multilayer structures. The structure supports a Fano resonance, which is about twice as sensitive to the refractive index changes in the surface layer, compared to the plasmonic mode in single nanohole arrays. A simplified STT-RAM multilayer of air/gold(5 nm)/MgO(10 nm)/gold(60 nm)/quartz substrate is considered as the platform for the dimer nanohole array. Our studies show that regarding the changes in the ultrathin MgO layer, the normalized figure of merit for this structure is up to more than 10 times larger than an array of single nanoholes. Furthermore, an improvement in bulk sensing performance over the array of nanohole heptamers is observed.

FRF: Toward Warp-Scheduler Friendly STT-RAM/SRAM Fine-Grained Hybrid GPGPU Register File Design

Modern graphics processing units (GPUs) exhibit increasing demands for register files (RFs) with larger capacity and bank sizes, which jeopardize the traditional SRAM-based RF designs due to their large die area and long access latency. Recent hybrid RF designs, e.g., SRAM and spin-transfer torque random access memory (STT-RAM)-based RFs, mitigate the issue by exploiting the density and performance advantages in STT-RAM and SRAM, respectively. However, existing hybrid RF designs adopt coarse integration that has limited write bandwidth between SRAM and STT-RAM, which restricts the adoption of different warp schedulers at runtime. In this article, we propose FRF, a warp-scheduler friendly fine-grained hybrid RF design using SRAM/STT-RAM hybrid cell (HC) structures. By integrating one SRAM cell and $N$ STT-RAM cells as one HC, FRF exploits internal write paths to enlarge the access bandwidth between SRAM and STT-RAM and thus greatly optimizes the area and performance. FRF enables the concurrent context-switching such that different warp schedulers may be adopted at runtime. FRF adopts interleaved register mapping (IRM) and on-demand register remapping to further improve the utilization of SRAM in each HC. Our experimental results show that, on average, FRF achieves 50% performance improvement and 40% energy consumption reduction over the coarse-grained hybrid design when adopting loose round-robin (LRR), and achieves 159% efficiency improvement over pure STT-RAM-based RF.

A Physics-Based Compact Model of Stochastic Switching in Spin-Transfer Torque Magnetic Memory

Spin-transfer torque random-access memory (STT-RAM) is gaining momentum as a promising technology for high-density and embedded nonvolatile memory. Owing to random thermal fluctuations, switching transitions generally display statistical variations from cycle to cycle. Stochastic variations are critical to the hindering of memory and computing applications of STT-RAM. To enable the design of STT-RAM circuits for memory and computing, there is a need for accurate compact models capable of predicting the stochastic behavior. Here, we present a detailed model accounting for the anomalous thermal regime of switching deviating from the Neel–Brown thermal model below 200 ns. Anomalous switching is explained by the nonlinear lowering of the energy barrier associated with the perpendicular magnetic anisotropy (PMA). The model is extensively verified against the write-error-rate (WER) data as a function of applied voltage and pulsewidth and experimental switching time-delay distributions.

Write Variation Aware Buffer Assignment for Improved Lifetime of Non-Volatile Buffers in On-Chip Interconnects

With multiple cores integrated on the same die, communication across cores is managed by on-chip interconnect called network-on-chip (NoC). Power and performance of these interconnect is a significant factor as the communication network consumes a considerable share of the power budget. In particular, the buffers used at every port of the NoC router consume considerable dynamic as well as static power. This paper attempts to reduce static power consumption by using non-volatile memory technology-based spin-transfer torque random access memory (STT-RAM) buffers. STT-RAM technology has the advantage of high density and low leakage but suffers from weaker write endurance. This impacts the lifetime of the router as a whole. The buffers in a router are allocated to virtual networks (VNets) and in-turn to virtual channels (VCs) within each VNet. To reduce uneven writes across the buffers, we propose policies to reduce intra-VNet write variation and inter-VNet write variation. The former performs write variation aware VC allocation in each VNet, and the latter does write variation aware buffer assignments to each VNet. Experimental evaluation on full system simulator shows that proposed policies reduce write variation to almost 0% and improve lifetime by 3.3 and 19.9 times for intra-VNet and inter-VNet, respectively. We also get significant gains in the energy delay product.

Write‐variation aware alternatives to replace SRAM buffers with non‐volatile buffers in on‐chip interconnects

With the advancement in CMOS technology and multiple processors on the chip, communication across these cores is managed by a network-on-chip (NoC). Power and performance of these NoC interconnects have become a significant factor.The authors aim to reduce the leakage power consumption of NoC buffers by the use of non-volatile spin transfer torque random access memory (STT-RAM)-based buffers. STT-RAM technology has the advantages of high density and low leakage but suffers from low endurance. This low endurance has an impact on the lifetime of the router on the whole due to unwanted write-variations governed by virtual channel (VC) allocation policies. Here various VC allocation policies that help the uniform distribution of the writes across the buffers are proposed. Iso-capacity and iso-area-based alternatives to replace SRAM buffers with STT-RAM buffers are also presented. Pure STT-RAM buffers, however, impact the network latency. To mitigate this, a hybrid variant of the proposed policies which uses alternative VCs made of SRAM technology in the case of heavy network traffic is proposed. Experimental evaluation of full system simulation shows that proposed policies reduce the write variation by 99% and improve lifetime by 3.2 times and 1093 times, respectively. Also a 55.5% gain in the energy delay product is obtained.

MLC STT-MRAM-Aware Memory Subsystem for Smart Image Applications

Next-generation memories with high storage capacity, high performance, and low power consumption are being researched due to the ever-growing demand for artificial intelligence and high-definition applications. Among such future memories, a multi-level cell (MLC) spin-transfer magnetic torque random access memory (STT-MRAM) attracts considerable attention as an alternative to static or dynamic random access memories. An MCL STT-MRAM has the advantages of capacity and non-volatility, but the disadvantages of performance, power consumption, and endurance resulting from complicated resistance state transition and detection processes. In particular, such issues are exacerbated in the latest smart image applications employing block-based processing algorithms. In this paper, we propose a memory subsystem that mitigates the MLC STT-MRAM disadvantages in smart image applications. Our main idea is threefold: MLC-aware image buffer composing, block-aware pixel-to-memory mapping, and prediction-aware image-to-buffer allocating techniques that all make multi-step resistance state transition and detection processes less required. Experimental results show that the proposed memory subsystem achieves 24.5% shorter application execution time, and 96.4% lower memory power consumption than the conventional memory subsystems for industrial smart image applications. In addition, our memory subsystem increases the lifetime of MLC STT-MRAMs via 93.8% fewer multi-step resistance state transition processes.

MFM and first order reversal curve (FORC) study of switching mechanism in Co25Pd75 films

Recent research on CoPd alloys with perpendicular magnetic anisotropy has suggested that they might be useful as the pinning layer in CoFeB/MgO-based perpendicular magnetic tunnel junctions for various spintronic applications such as spin-torque transfer random access memory. We have previously studied the effect of seed layer and composition on the structure (by XRD, SEM, AFM, and TEM) and the performance (coercivity) of these CoPd films. These films do not switch coherently, so the coercivity is determined by the details of the switching mechanism, which was not studied in our previous paper. In the present paper, we show that information can be obtained about the switching mechanism from magnetic force microscopy (MFM) together with first order reversal curves, despite the fact that MFM can only be used at the zero field. We find that these films switch by a mechanism of domain nucleation and dendritic growth into a labyrinthine structure, after which the unreversed domains gradually shrink to small dots and then disappear.