Abstract
STT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based on-chip caches. Due to its high density and low leakage power, STT-RAM can be used to build massive capacity last-level caches (LLC). Unfortunately, STT-RAM has a much longer write latency and a much greater write energy than SRAM. Researchers developed hybrid caches made up of SRAM and STT-RAM regions to cope with these challenges. In order to store as many write-intensive blocks in the SRAM region as possible in hybrid caches, an intelligent block placement policy is essential. This paper proposes an adaptive block placement framework for hybrid caches that incorporates metadata embedding (ADAM). When a cache block is evicted from the LLC, ADAM embeds metadata (i.e., write intensity) into the block. Metadata embedded in the cache block are then extracted and used to determine the block’s write intensity when it is fetched from main memory. Our research demonstrates that ADAM can enhance performance by 26% (on average) when compared to a baseline block placement scheme.
Highlights
Modern processors use on-chip multi-level caches to compensate for main memory systems’ restricted latency and bandwidth
We make two key observations about write intensity and re-fetch rate of cache blocks; We propose a new adaptive block placement framework for hybrid caches based on a metadata embedding technique
We propose ADAM, an adaptive block placement framework with metadata embedding in order to fully exploit the benefits of hybrid caches
Summary
Modern processors use on-chip multi-level caches to compensate for main memory systems’ restricted latency and bandwidth. The ever-expanding working set of modern applications, as well as their bandwidth demands, necessitates industry manufacturers in providing larger on-chip last-level caches (LLC). Due to its high power consumption and low density, Static Random Access Memory (SRAM), the traditional memory technology for LLCs, does not scale well. Numerous researchers are looking into non-volatile memory technologies such as Spin-Transfer Torque RAM (STT-RAM) as a potential replacement for SRAM. STT-RAM is appealing because it has a higher density and lower leakage power consumption than SRAM, allowing it to scale more efficiently. Spin-Transfer Torque Random Access Memory (STT-RAM) is a dense non-volatile memory technology [1,2]. We can use one of two states of the MTJ to represent logic ‘0’ or ‘1’
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