Spin Transfer Torque Magnetic Tunnel Junction Research Articles

Hardware Security Exploiting Post-CMOS Devices: Fundamental Device Characteristics, State-of-the-Art Countermeasures, Challenges and Roadmap

Emerging nanoelectronic semiconductor devices have been quite promising in enhancing hardware-oriented security and trust. However, implementing hardware security primitives and methodologies requires large area overhead and power consumption. Furthermore, emerging new attack models and vulnerabilities are regularly evolving and cannot be adequately addressed by current CMOS technology. This paper for the first time presents a comprehensive review of numerous post-CMOS technologies based hardware security primitives and methodologies, particularly true random number generators, physically unclonable functions, sidechannel analysis countermeasures, and hardware obfuscation techniques. Various beyond-CMOS device technologies including tunneling FET (TFET), hybrid phase transition FET (HyperFET), carbon nanotube FET (CNTFET), silicon nanowire FET (SiNWFET), symmetrical tunneling FET (SymFET), phase-change memory (PCM), spin-transfer torque magnetic tunnel junction (STT-MTJ), resistive random access memory (RRAM) have been considered in this study. First, the basic principle of operation and unusual characteristics of nanoelectronic devices used for hardware security applications have been extensively discussed. Later, CMOS technology challenges and benefits of emerging nanotechnologies for the design of hardware security primitives and methodologies have been reported. Finally, different analyses have been presented to demonstrate the promising performance of post-CMOS devices over the current CMOS technology in different countermeasures. Additionally, challenges, future directions, and plans have been presented to achieve more research outcomes in this field.

A novel self write-terminated driver for hybrid STT-MTJ/CMOS LIM structure

A novel self write-terminated driver is proposed for the hybrid spin transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS circuits based on logic-in-memory (LIM) structure. Using continuous write monitoring mechanism, the novel circuitry completely eliminates the unnecessary flow of write current which abolishes the wastage of write energy in the proposed write driver. Hence, the total energy required for writing process is reduced noticeably by 63.32% in novel write driver compared to the conventional write circuit. Monte-Carlo simulation is then performed by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ. Simulations are also carried out for the proposed write driver, by varying the transistor sizes and supply voltage to analyze its switching probability to obtain safe operating region. Further, the proposed write driver is integrated with hybrid full adder to demonstrate its feasibility in low-power VLSI circuits.

Calibration and Parameter Extraction of STT-MTJ Device at High Frequency by Using De-Embedding Approach Based on TRL Calibration

Spin-Torque-Transfer Magnetic Tunnel Junction (STT-MTJ) device shows wide applications in many important scenarios, including magnetic random access memory (MRAM), logic design, and high-frequency application. Its characterizations at the high frequency are studied intensively recently. In this article, the high-frequency properties of the STT-MTJ device are investigated thoroughly, including a de-embedding approach followed by an extraction procedure for removing the influences from the environment and the package. The de-embedding approach is performed on the STT-MTJ device operated at a high frequency, which can be used to calibrate its electrical characteristics by eliminating the environmental influence. After the calibration, the equivalent circuit for the MTJ device at high frequency can be set up, followed by the extraction procedure of the parasitic parameters of the high-frequency-equivalent-circuit. Combined with the extracted parameters, the equivalent circuit can be used for the simulation work with the MTJ device involved in the high-frequency operation.

Analysis of State-of-the-Art Spin-Transfer-Torque Nonvolatile Flip-Flops Considering Restore Yield in the Near/Sub-Threshold Voltage Region

Recently, the leakage power consumption of Internet of Things (IoT) devices has become a main issue to be tackled, due to the fact that the scaling of process technology increases the leakage current in the IoT devices having limited battery capacity, resulting in the reduction of battery lifetime. The most effective method to extend the battery lifetime is to shut-off the device during standby mode. For this reason, spin-transfer-torque magnetic-tunnel-junction (STT-MTJ) based nonvolatile flip-flop (NVFF) is being considered as a strong candidate to store the computing data. Since there is a risk that the MTJ resistance may change during the read operation (i.e., the read disturbance problem), NVFF should consider the read disturbance problem to satisfy reliable data restoration. To date, several NVFFs have been proposed. Even though they satisfy the target restore yield of 4σ, most of them do not take the read disturbance into account. Furthermore, several recently proposed NVFFs which focus on the offset-cancellation technique to improve the restore yield have obvious limitation with decreasing the supply voltage (VDD), because the offset-cancellation technique uses switch operation in the critical path that can exacerbate the restore yield in the near/sub-threshold region. In this regard, this paper analyzes state-of-the-art STT-MTJ based NVFFs with respect to the voltage region and provides insight that a simple circuit having no offset-cancellation technique could achieve a better restore yield in the near/sub-threshold voltage region. Monte–Carlo HSPICE simulation results, using industry-compatible 28 nm model parameters, show that in case of VDD of 0.6 V, complex NVFF circuits having offset tolerance characteristic have a better restore yield, whereas in case of VDD of 0.4 V with sizing up strategy, a simple NVFF circuit having no offset tolerance characteristic has a better restore yield.

SEU Mechanisms in Spintronic Devices: Critical Parameters and Basic Effects

This article investigates radiation-induced switching mechanisms, temperature effects, breakdown voltage, sensitive volume, and critical charge definitions for spin-transfer torque magnetic tunnel junctions. The thermal spike model is adopted to estimate the temperature reached during heavy-ion irradiation, and temperature effects are suggested to be responsible for the magnetic properties' degradation and for upset processes.

Ultra-High-Performance Magnetic Nonvolatile Level Converter Flip-Flop with Spin-Hall Assistance for Dual-Supply Systems with Power Gating Architecture

Recently, nonvolatile spintronic memory elements have drawn a lot of attention for designing nanoscale integrated circuit design due to their several advantages such as near-zero static power, high endurance, good scalability, and compatibility with the current process technologies. In this paper, a high-speed and low-power spintronic-based nonvolatile level converter flip-flop (NVLCFF) is proposed. This efficient design facilitates the use of power gating and dual-supply techniques simultaneously for ultra-energy-efficient integrated circuits. The proposed NVLCFF uses the spin Hall effect-assisted spin-transfer torque magnetic tunnel junction (SHE-assisted STT-MTJ) to provide nonvolatile data storage. Furthermore, a new voltage level converter is presented to perform voltage level conversion in the proposed NVLCFF. Elimination of the contention condition, using one reconfigurable MTJ, and no static voltage division in the proposed design lead to considerably higher speed and lower power. The 7-nm FinFET, as one of the leading industrial technologies, is utilized to design the peripheral circuity. The HSPICE simulation results show on average, 64%, 62%, and 35% improvements regarding the power dissipation, backup energy, and restore energy as compared to the other NVLCFFs. Furthermore, comprehensive Monte Carlo simulations demonstrate the robustness of the proposed design in the presence of process variations.

Design of an MTJ/CMOS-Based Asynchronous System for Ultra-Low Power Energy Autonomous Applications

Most of today’s IoT-based computing systems offer an opportunity to build smarter systems for application areas such as healthcare monitoring and wireless sensor nodes. Since these systems are energy limited and remain idle for most of the time, they suffer from large leakage power dissipation. Another problem faced by such computing systems is sporadic power failures when employed with energy harvesters where the system loses its current state and needs long reinitialization time. To address these problems, this work combines asynchronous design techniques with nonvolatility to achieve ultra-low power operation during active mode and data retention during power failure. This paper first presents a detailed analysis of different implementations of volatile c-element and compares their performance in terms of power and delay. Then one of the implementations is selected for nonvolatile design of a hybrid c-element using emerging spin transfer torque–magnetic tunnel junction (STT–MTJ) technology which allows energy-efficient data retention during idle mode/power-off mode and during sudden power failures. Using this hybrid c-element, we design a novel nonvolatile weak conditioned half-buffer. The extensive analysis of these designs with different design metrics is performed at the circuit level using Synopsys HSPICE circuit simulator.

A VLSI Majority-Logic Device Based on Spin Transfer Torque Mechanism for Brain-Inspired Computing Architecture

This article presents a majority-logic device, called sttMAJ, based on spin-transfer torque magnetic tunnel junctions (STT-MTJs). sttMAJ devices make it possible to build Boolean and non-Boolean circuits without any transistors. We leverage a physics-based model of sttMAJ device to the design of different highly scalable current-mode logic circuits and neuromorphic-computing/image-processing applications. The functionality of sttMAJ-based circuits is verified using the SPICE circuit simulator. The simulation results reveal that the gate device not only provides a simple and powerful structure (in terms of implementing digital functions and image-processing applications with a small number of devices) but also offers high performance due to its better electrical properties.

Spin-Transfer Torque Magnetic Tunnel Junction for Single-Event Effects Mitigation in IC Design

For embedded systems in harsh environments, a radiation robust circuit design is still an open challenge. As complementary–metal–oxide semiconductor (CMOS) processes get denser and smaller, their immunity toward particle strikes decreases drastically. Due to its good radiation effects tolerance and its inherent nonvolatility, spin-transfer torque magnetic tunnel junction (STT-MTJ) is considered a promising candidate for high-reliability electronics. Nevertheless, when integrated in a CMOS circuit, these magnetic devices could still be affected by upsets. To decrease the probability of this occurrence, a radiation robust setup is used to calibrate a physics-based 20-nm MTJ compact model, integrated in a 28-nm Fully Depleted Silicon On Insulator (FD-SOI) technology. Thus, a radiation hardening by design (RHBD) solution is presented, where a nonvolatile sequential block enables one to mitigate the single-event effects (SEEs).

Energy-efficient data retention in D flip-flops using STT-MTJ

PurposeEmerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention.Design/methodology/approachThe conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state.FindingsA comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption.Originality/valueTwo novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.

An Asynchronous and Low-Power True Random Number Generator Using STT-MTJ

The emerging spin-transfer torque magnetic tunnel junction (STT-MTJ) technology exhibits interesting stochastic behavior combined with small area and low operation energy. It is, therefore, a promising technology for security applications, specifically the generation of random numbers. In this paper, STT-MTJ is used to construct an asynchronous true random number generator (TRNG) with low power and a high entropy rate. The asynchronous design enables the decoupling of the random number generation from the system clock, allowing it to be embedded in low-power devices. The proposed TRNG is evaluated by a numerical simulation, using the Landau–Lifshitz–Gilbert (LLG) equation as the model of the STT-MTJ devices. Design considerations, attack analysis, and process variation are discussed and evaluated. We show that our design is robust to process variation, thus achieving an entropy generating rate between 99.7 and 127.8 Mb/s with 6–7.7 pJ per bit for 90% of the instances.

Design A High Speed Spin-Torque Transfer Magnetic Tunnel Junction (Stt-Mtj) Non-Volatile Flip-Flops Based On Memory

Basically, in low power applications, the energy should be harvested depend on the frequent interruptions. In this paper we proposed the design of spin-transfer torque magnetic tunnel junctions (STT-MTJs) non volatile based on flip flops based memory. The main intent of non volatile is to address the state of system by saving the memory. By using STT-MTJs based flip flop, high energy consumption will be obtained and there will be backup of the system. In CMOS the flip flop will used standard magnetic MRAM technology. The main intent of magnetic tunnel junctions is to store the data. The proposed non volatile flip flop will determine the delay and energy. Logic circuits are enabled using non volatility and this will reduce the start up latency. This start up latency ranges from micro seconds to hundred pico seconds. Here the information is stored using non volatile logic of memory. This process is done on pre chip basis. Hence compared to existed system, the proposed system gives effective results.

A theoretical study of switching energy efficiency in sub-10-nm spintronic devices

Spin-transfer torque (STT) magnetic tunnel junctions (MTJs) in the sub-10-nm size range have shown enhancement in energy efficiency. This improved switching energy efficiency means a longer spin relaxation time, a corresponding stronger spin accumulation, and a resulting lower switching current density. This improvement in switching energy efficiency stems from a reduction in damping as the device size is reduced. This can be seen by a reduction in the damping constant in the Landau-Lifshitz Gilbert (LLG) equation. This term can take a range of values, and this range depends on the different contributions from the surface relative to the bulk. Specifically, at such small sizes the damping constant differs from the bulk damping constant. In this study, a detailed equation defining this surface-to-volume relative contribution was developed. This theory was tested through simulations involving a sub-10-nm cobalt cube utilizing the Object Oriented Micromagnetic Framework (OOMMF). These simulations showed a longer spin relaxation time with a decrease in device size (defined by side length) as well as a reduction in switching current density with a decrease in side length. This reduction in switching current density was approximately logarithmic versus volume, surface area, and side length. Moreover, in the sub-5-nm range, this reduction was nearly linear with respect to side length. These results agree with theoretical predictions and they are aligned with the experimentally demonstrated quantum size effect.

High-Entropy STT-MTJ-Based TRNG

Hardware true random number generators (TRNGs) yield random numbers from physical processes. Traditionally, such devices are based on statistically random events such as thermal noise or other quantum phenomena. In this brief, we propose a novel TRNG design using a spin-transfer torque magnetic tunnel junction (MTJ) device. Our solution exploits the stochastic nature of the MTJ switching, and the behavior of an XOR gate dealing with probabilistic signals. We show that by using multiple MTJ devices, the proposed TRNG succeeds in filtering the negative effect of environmental changes as well as fabrication-induced variability and generates random sequences with high-entropy under any conditions.

Nanomagnetic Particle-Based Information Processing

Understanding the physics of spintronic devices in the 3-nm size range can pave the way to next-generation energy-efficient information processing devices. To build a spin computer, a layer of 3-nm CoFe 2 O 4 nanoparticles was sandwiched as a central layer into the standard spin-transfer torque magnetic tunneling junction (STT-MTJ) stack. With further focused ion beam (FIB) trimming, a dual-layer junction consisting of one or more nanoparticles separating two CoFeB ferromagnetic layers was turned into a two-terminal spintronic device. The measured room-temperature electron transport through the device showed a staircase effect reminiscent of a single electron transport, which in addition depended on the relative orientations of the magnetic states of the ferromagnetic layers and the high-anisotropy ferrimagnetic nanoparticle. Besides having the staircase steps, the V-I curve indicated switching of the nanoparticles magnetization through the STT effect at currents of above 0.05 uA. The magnetoresistance (MR) curve of this device with the magnetic field applied perpendicular to the junction had an anomalous oscillatory field dependence in a relatively low field range of below 100 Oe.

Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration

In this paper, we discuss the potential foundry announced integration of magnetic random access memory (MRAM) on fully depleted silicon-on-insulator (FDSOI). The spin transfer torque magnetic tunnel junction (STT-MTJ) and the next-generation voltage-controlled magnetic anisotropy MTJ are separately integrated into a 28-nm FDSOI process as the MRAM or magnetoelectric random access memory (MeRAM)-on-FDSOI integration. Micromagnetic and electrical simulations are used to evaluate the performance of hybrid circuits. Circuit-level design strategies are explored that use FDSOI leverage and spin-device characteristic to realize writing and sensing power-delay efficiency, robust, and reliable performance in the one-transistor one-MTJ MRAM/MeRAM bit-cell and sensing circuits. Reliability issues are discussed. Process variation and aging resilience strategies, e.g., step-wise back-bias, flip-well re-configuration, and write assist, are proposed to address failure and aging degradation in the MRAM/MeRAM-on-FDSOI integration. A qualitative summary demonstrates that the MRAM/MeRAM-on-FDSOI integration offers attractive performance for future non-volatile CMOS integration.

Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic

Systems powered by harvested energy must consume very low power and withstand frequent interruptions in power. Nonvolatile logic (NVL) addresses the latter by saving the system state in flipflops enhanced with spin-transfer torque magnetic tunnel junctions (STT-MTJs) as the nonvolatile storage devices. Manufacturing variations in the STT-MTJs and in CMOS transistors significantly reduce yield, leading to overdesign and high-energy consumption. A detailed analysis of the design tradeoffs in the driver circuitry for performing backup and restore, and a novel method to design the energy optimal driver for a given yield is presented. Next, efficient designs of two nonvolatile flip-flop (NVFF) circuits are presented, in which the backup time is determined on a per-chip basis, resulting in minimizing the energy wastage and satisfying the yield constraint. To achieve a yield of 98%, the conventional approach would have to expend nearly $5\times $ more energy than the minimum required, whereas the proposed tunable approach expends only 26% more energy than the minimum. Also included are the energy consumption of the proposed NVFF designs when used in two larger function blocks. Experimental results were based on a commercial 40-nm process design kit, and HSPICE simulations with foundry supplied statistical models and data.

Fully Nonvolatile and Low Power Full Adder Based on Spin Transfer Torque Magnetic Tunnel Junction With Spin-Hall Effect Assistance

As technology node scales down below 90 nm, the conventional complementary metal oxide semiconductor (CMOS) logic circuits suffer from various problems such as high standby power due to increase in leakage current. Spintronic devices based on magnetic tunnel junction (MTJ) is one of the most promising technology candidates for the future of the digital circuits. MTJ-based logic circuits can offer nonvolatility, high endurance, high density, low standby power dissipation, and 3-D integration capability with the CMOS technology. In recent years, several full-adder circuits are proposed based on MTJs that are not fully nonvolatile since they use MTJs to store only one of their inputs. This paper proposes a fully nonvolatile magnetic full-adder (MFA) circuit offering the capability of power gating with no loss of data. The proposed circuit stores all the inputs in MTJs using the spin-transfer torque (STT) method assisted by the spin-Hall effect (SHE). Thanks to the SHE assistance, delay and power consumption of the MTJ switching are reduced significantly. Moreover, as a result of lower write current, the endurance of the oxide barrier can be increased. Using a three-terminal SHE–STT–MTJ model and a 45 nm CMOS SPICE model, we simulated and validated the functionality of our design and compared it with some recent previous MFAs. Simulation results reveal that the proposed MFA offers considerable superiorities over the recent counterparts.

Variation-Resilient True Random Number Generators Based on Multiple STT-MTJs

In the Internet of Things era, security concerns may require a cryptography system in every connected device. True random number generators (TRNGs) are preferred instead of pseudorandom number generators in the cryptography systems to achieve a higher level of security. For on-chip applications, we seek scalable and CMOS-compatible devices and designs for TRNGs. In this paper, the stochastic behavior of the spin transfer torque magnetic tunnel junction (STT-MTJ) is utilized for the source of randomness. However, variations and correlations exist in MTJs due to fabrication limitations, so TRNG designs based on a single MTJ have to be postprocessed or tracked in real time to ensure an acceptable level of randomness. Two novel designs are proposed in this paper, which can produce random sequences with high variation resilience. The first design uses a parallel structure to minimize variation effects, and the second design leverages the symmetry of an MTJ pair to take advantage of any correlations. Moreover, a universal circuit for quality improvement is proposed and it can be used with any random number generator. All of the designs are validated in a 28-nm CMOS process by Monte Carlo simulation with a compact model of the MTJ. The National Institute of Standards and Technology (NIST) statistical test suite is used to test the randomness quality of the generated sequences under the scenario of encryption keys in the transport layer security or secure sockets layer (TLS/SSL) cryptographic protocol.

3D multilevel spin transfer torque devices

Spin-transfer torque magnetic tunneling junction devices capable of a multilevel three-dimensional (3D) information processing are studied in the sub-20-nm size range. The devices are built using He+ and Ne+ focused ion beam etching. It has been demonstrated that due to their extreme scalability and energy efficiency, these devices can significantly reduce the device footprint compared to the modern CMOS approaches and add advanced features in a 3D stack with a sub-20-nm size using a spin polarized current.