Abstract

In the Internet of Things era, security concerns may require a cryptography system in every connected device. True random number generators (TRNGs) are preferred instead of pseudorandom number generators in the cryptography systems to achieve a higher level of security. For on-chip applications, we seek scalable and CMOS-compatible devices and designs for TRNGs. In this paper, the stochastic behavior of the spin transfer torque magnetic tunnel junction (STT-MTJ) is utilized for the source of randomness. However, variations and correlations exist in MTJs due to fabrication limitations, so TRNG designs based on a single MTJ have to be postprocessed or tracked in real time to ensure an acceptable level of randomness. Two novel designs are proposed in this paper, which can produce random sequences with high variation resilience. The first design uses a parallel structure to minimize variation effects, and the second design leverages the symmetry of an MTJ pair to take advantage of any correlations. Moreover, a universal circuit for quality improvement is proposed and it can be used with any random number generator. All of the designs are validated in a 28-nm CMOS process by Monte Carlo simulation with a compact model of the MTJ. The National Institute of Standards and Technology (NIST) statistical test suite is used to test the randomness quality of the generated sequences under the scenario of encryption keys in the transport layer security or secure sockets layer (TLS/SSL) cryptographic protocol.

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