Spin Transfer Torque Magnetic Tunnel Junction Research Articles

In-sensor nonlinear convolutional processing based on hybrid MTJ/CMOS arrays

In-sensor computing implemented by novel neuromorphic devices has been regarded as the potential technology to break the acquisition wall. Moreover, the nonlinear convolution inspired by the biological neural system outperforms the traditional linear convolution. Therefore, realizing the in-sensor nonlinear convolutional processing with the intrinsic nonlinearity of novel neuromorphic devices would be exciting and hardware friendly. Here, a new type of in-sensor nonlinear convolutional processing architecture is proposed based on STT-MTJ (spin transfer torque-magnetic tunnel junction) devices and simple peripheral circuits. The nonlinear dynamic characters of the STT-MTJ device are regulated by bias currents and magnetic fields. Meanwhile, the hybrid STT-MTJ/CMOS (complementary metal oxide semiconductor) circuit exhibits nonlinear dependence of the output voltage on bias currents and magnetic fields. In this way, a nonlinear convolutional unit is developed by the inherent property of hardware. Based on the in-sensor nonlinear convolutional unit, a convolutional network is simulated to perform the classification task, and a high accuracy is realized. This work indicates that the in-sensor nonlinear convolution offers a promising way to develop in-sensor computing at the edge intelligence devices.

Realization of Artificial Neurons and Synapses Based on STDP Designed by an MTJ Device.

As the third-generation neural network, the spiking neural network (SNN) has become one of the most promising neuromorphic computing paradigms to mimic brain neural networks over the past decade. The SNN shows many advantages in performing classification and recognition tasks in the artificial intelligence field. In the SNN, the communication between the pre-synapse neuron (PRE) and the post-synapse neuron (POST) is conducted by the synapse. The corresponding synaptic weights are dependent on both the spiking patterns of the PRE and the POST, which are updated by spike-timing-dependent plasticity (STDP) rules. The emergence and growing maturity of spintronic devices present a new approach for constructing the SNN. In the paper, a novel SNN is proposed, in which both the synapse and the neuron are mimicked with the spin transfer torque magnetic tunnel junction (STT-MTJ) device. The synaptic weight is presented by the conductance of the MTJ device. The mapping of the probabilistic spiking nature of the neuron to the stochastic switching behavior of the MTJ with thermal noise is presented based on the stochastic Landau-Lifshitz-Gilbert (LLG) equation. In this way, a simplified SNN is mimicked with the MTJ device. The function of the mimicked SNN is verified by a handwritten digit recognition task based on the MINIST database.

TEMT: A Transient Electronic–Magnetic–Thermal-Coupled Simulation Framework for STT-MTJs

Being a promising candidate for future non-volatile memory and neuromorphic computing, Spin-Transfer-Torque Magnetic Tunnel Junction (STT-MTJ) devices are gaining substantial momentum in industrial adoption in recent years, calling for EDA support for higher modeling capabilities. However, the complex interplay of multiple physical mechanisms featured in MTJ devices impose substantial challenges to their numerical modeling. In this work, we propose a fully coupled, transient electronic-magnetic-thermal (TEMT) modelling approach for STT-MTJ devices. Aiming to be first-principle and physically holistic, TEMT combines the atomistic non-equilibrium Green’s function (NEGF) model for tunneling currents, the Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation for magnetic dynamics and the heat conduction equation (HCE) for thermal dynamics in a self-consistent manner. To alleviate computational burden, we also devise an analytical approximation approach to reduce the number of NEGF solutions in the TEMT framework, which leads to over 15X speed-up with a very mild accuracy loss. An in-depth investigation of STT-MTJ devices using the TEMT framework is conducted to demonstrate its benefits and performance.

A binarized spiking neural network based on auto-reset LIF neurons and large signal synapses using STT-MTJs

A binarized spiking neural network using auto-reset leaky integrate-and-fire neurons with a two-transistor and three-magnetic tunnel junction core and large signal synapses with two-transistor and two-magnetic tunnel junctions is designed. The network is applied to a classifier of the MNIST handwritten digit dataset with a 784 × 400 synapse crossbar array. The weights are trained offline using the spike-timing-dependent plasticity learning algorithm and deployed to the spin-transfer torque magnetic tunnel junction (STT-MTJ) resistances in the synapses after being binarized. Its performance is evaluated by HSPICE using the STT-MTJ device model, which takes the stochastic change in the angle between the two magnetic moments in the free and pinned layers into consideration. 75% test accuracy is achieved for 1200 patterns with 1 ns read and 1 ns write operations and 0.23 pJ/SOP energy consumption.

A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops

While the spin-transfer torque (STT) magnetic tunnel junction (MTJ) is a promising technique for enabling nonvolatile flip-flops (NVFFs) to perform power gating to reduce leakage power without any data losses, the large store energy (the energy to make a store operation) of MTJs needs to be addressed. The nonvolatile cool mega array series is an edge-oriented coarse-grained reconfigurable accelerator that implements an improved MTJ-based NVFF with a verify-and-retryable store method that should ideally reduce the store energy under the presence of the switching time variation originating from the stochastic nature of the MTJs. However, the energy reduction effect of the method has not been formulated or evaluated thoroughly enough to make the best use of the method in actual applications. In this study, we propose an analytical model to estimate the store energy in typical operational conditions under the assumption of switching time variations following the normal distributions based on the measurements of a real chip fabricated with a 40-nm perpendicular MTJ/CMOS hybrid process. In contrast to the tedious measurement on each different condition, the proposed model allows for an instantaneous determination of the best storing method for minimizing the store energy, with an energy reduction of up to 69% compared with a conventional one-time attempt storing method. This model is expected to be used for system-level energy simulations and, ultimately, for design explorations in pursuit of energy-optimized memory.

AM4: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing

In-memory computing seeks to minimize data movement and alleviate the memory wall by computing in-situ, in the same place that the data is located. One of the key emerging technologies that promises to enable such computing-in-memory is spin-transfer torque magnetic tunnel junction (STT-MTJ). This paper proposes AM4, a combined STT-MTJ-based Content Addressable Memory (CAM), Ternary CAM (TCAM), approximate matching (similarity search) CAM (ACAM), and in-memory Associative Processor (AP) design, inspired by the recently announced Samsung MRAM crossbar. We demonstrate and evaluate the performance and energy-efficiency of the AM4-based AP using a variety of data intensive workloads. We show that an AM4-based AP outperforms state-of-the-art solutions both in performance (with the average speedup of about 10 ×) and energy-efficiency (by about 60 × on average).

Non-Volatile Logic Design Considerations for Energy Efficient Tolerant Variation

Systems design for the non-volatile application must work on less energy or power. The spin-transfer torque-magnetic tunnel junction (STT-MTJ) devices added to the flip-flops which are regarded as non-volatile storage devices. Those are addresses to save the energy of that system stated by the nonvolatile logic. The changes during the production of STT-MTJ and CMOS transistors decrease the yield, which leads to overdesign as well as more energy consumption. The total processes of driver circuitry design for the tradeoffs for backup and restore performance. A new method called the novel method is introduced for flawless energy drivers for given results. The design for the backup time determination and to reduce the energy wastage are mentioned. To get an efficient output of 98% this approach needs to dissipate 5 times more energy than initially required. This method can dissipate the energy up to 26%. It also contains the nonvolatile flip-flop (NVFF) which has energy consumption more when it is used in the functional blocks.

Emerging tunnel FET and spintronics-based hardware-secure circuit design with ultra-low energy consumption

Present complementary metal–oxide–semiconductor (CMOS) technology with scaled channel lengths exhibits higher energy consumption in designing secure electronic circuits against hardware vulnerabilities and breaches. Specifically, CMOS sense amplifier-based secure differential power analysis (DPA) countermeasures at scaled channel lengths show large energy consumption, with increased vulnerability. Additionally, spin-transfer torque magnetic tunnel junction (STT-MTJ) and CMOS-based logic-in-memory (LiM) cells demonstrate high energy consumption due to the large write current requirement of the STT-MTJ and poor MOS device performance at scaled channel lengths. This paper for the first time leverages emerging tunnel field effect transistor (TFET) steep-slope device characteristics and compatible non-volatile STT-MTJ devices for enhanced hardware security with ultra-low energy consumption at lower supply voltages. TFET-based sense amplifier-based logic (SABL) gates are proposed that achieve 3× lower energy consumption than the Si FinFET SABL designs. Further, utilizing TFET SABL gates, a TFET PRIDE S-box is designed that exhibits higher DPA resilience with 3.2× lower energy consumption than the FinFET designs. With the resulting lower static power consumption, TFET SABL-based cryptosystems are thus less vulnerable to static power side-channel attacks. Additionally, the proposed STT-MTJ and TFET LiM gates achieve 4× lower energy consumption than the STT-MTJ and FinFET designs. Lastly, these gates are explored in a logic encryption/locking technique that shows 3.1× lower energy consumption than the STT-MTJ and FinFET-based design.

A process variation resilient spintronic true random number generator for highly reliable hardware security applications

True random number generators (TRNGs) are critical in cryptography and security systems. This paper presents a reliable TRNG relying on the stochastic switching of the spin-transfer torque magnetic tunnel junction (STT-MTJ) in the sub-critical current regime. Using an XOR-based structure in our proposed design eliminates the need for succeeding post-processing units while ensuring a reliable generation of random numbers, even in the presence of major variations. Moreover, utilizing gate-all-around (GAA) carbon nanotube field-effect transistors (CNTFETs) and the efficient structure of the proposed design leads to a low-power and high-performance operation. Comprehensive transient simulations verify the functionality of the proposed TRNG in fabrication process corners. According to the simulation results, our proposed TRNG has, on average, 53% and 63% lower power consumption and energy per bit, respectively, and a 70% smaller area compared to its counterparts. A statistical randomness test provided by the U.S. National Institute of Standards and Technology (NIST) validates the randomness quality of the generated random bitstreams.

Fully Nonvolatile Hybrid Full Adder Based on SHE+STT-MTJ/CMOS LIM Architecture

Emerging hybrid spin-Hall-effect-assisted+spin transfer torque-magnetic tunnel junction (SHE+STT-MTJ)/CMOS logic-in-memory (LIM) architecture is considered as the promising next-generation candidate for the future digital integrated circuits. It overcomes the limitations of von Neumann architecture such as memory wall and also rises in the standby mode energy consumption. There are several full adder (FA) circuits based on the LIM architecture, which are either fully nonvolatile (NV) or partially NV. As the main disadvantage, these circuits suffer from wastage of write energy during the MTJ writing process. Furthermore, the existing fully NVFA can be used only for approximate computing. Hence, in this article, we have proposed fully NVFA for exact computation with self-write-termination read-write (SWTRW) circuitry. In SWTRW circuitry, wastage of write energy is eliminated due to a continuous monitoring (CM) and self-write-termination (SWT) process which saves a significant amount of energy of 95.88%. With the adaption of an improved sense amplifier, the NVFA developed in this article saves energy of 88.1% during computation/reading compared with its conventional counterpart. To add on, writing and reading the energy delay product (EDP) are also reduced by 90.56% and 78.76%, respectively.

Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing

Smart material implication (SIMPLY) logic has been recently proposed for the design of energy-efficient Logic-in-Memory (LIM) architectures based on non-volatile resistive memory devices. The SIMPLY logic is enabled by adding a comparator to the conventional IMPLY scheme. This allows performing a preliminary READ operation and hence the SET operation only in the case it is actually required. This work explores the SIMPLY logic scheme using nanoscale spin-transfer torque magnetic tunnel junction (STT-MTJ) devices. The performance of the STT-MTJ based SIMPLY architecture is analyzed by varying the load resistor and applied voltages to implement both READ and SET operations, while also investigating the effect of temperature on circuit operation. Obtained results show an existing tradeoff between error rate and energy consumption, which can be effectively managed by properly setting the values of load resistor and applied voltages. In addition, our analysis proves that tracking the temperature dependence of the MTJ properties through a proportional to absolute temperature (PTAT) reference voltage at the input of the comparator is beneficial to mitigate the reliability degradation under temperature variations.

A Spintronic In-Memory Computing Network for Efficient Hamming Codec Implementation

Hamming code is a linear error correcting code that is widely used in memory and communication systems. In general, a codec hardware is required to encode or decode the information. In this brief, we propose for the first time a spintronic in-memory computing (IMC) network consisting of magnetic tunnel junctions (MTJs) for Hamming codec hardware implementation. Such an IMC network stores the generation matrix or parity-check matrix in a spin transfer torque (STT) MTJ array and performs vector matrix multiplication (VMM) with modulo-2 to generate desired codewords or syndrome-vectors during the encoding or decoding process, respectively. The output results are represented by the states of the spin orbit torque (SOT) MTJs, which can unipolarly flip based on the modulo-2 VMM results. Based on our developed physics-based STT and SOT MTJ SPICE models, we verified the functionality and evaluated the performance of the design in the 40nm technology node. The simulation results show that our work can generate codewords and syndrome-vectors with much lower (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> –10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> times) energy consumption compared to state-of-the-art designs based on memristor network, CPU and GPU.

Design and Performance Benchmarking of Hybrid Tunnel FET/STT-MTJ-Based Logic In-Memory Designs for Energy Efficiency

With CMOS technology scaling and increased short channel effects, spin-transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS-based logic-in-memory (LIM) designs consume significantly higher energy at scaled supply voltages. To enhance the energy efficiency of LIM circuit designs, this work proposes a hybrid tunnel FET (TFET)/MTJ-based digital circuit design approach at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathbf {DD}} = 0.3$ </tex-math></inline-formula> V. A Schmitt triggered pre-charge sense amplifier (ST-PCSA) with a strong feedback mechanism at the pull-down section is considered in TFET/MTJ-based LIM designs. The proposed LIM-MTJ designs are implemented using 20 nm TEFT technology and perpendicular anisotropy CoFeB/MgO/CoFeB MTJs. Two input and, or, xor logic gates, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times1$ </tex-math></inline-formula> multiplexer, 1-bit magnetic full adder (MFA), 4-bit magnetic ripple carry adder (RCA), and a simple 1-bit magnetic arithmetic and logical unit (M-ALU) are designed, exploring the proposed ST-PCSA-based hybrid TFET/MTJ logic. The proposed ST-PCSA-based hybrid TFET/MTJ LIM designs achieve ~47.2%–55.55% lower energy consumption in comparison with the PCSA-based TFET/MTJ LIM designs. Performance benchmarking with 20 nm FinFET designs demonstrates that the proposed TFET/MTJ LIM designs achieve 11.1%–25.9% lower energy consumption when compared with equivalent FinFET/MTJ-based LIM designs.

Design and Evaluation of a Self Write-Terminated Hybrid MTJ/CMOS Full Adder Based on LIM Structure

In this paper, a power-efficient self write-terminated hybrid full-adder (SWTHFA) has been developed using the self write-terminated write driver and an improved version of the sense amplifier already reported in the literature. The SWTHFA is designed using hybrid spin transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS circuit based on logic-in-memory architecture. The use of a modified sense amplifier improves the power dissipation and output response on one hand, whereas, on the other hand, self-write-terminated write driver cuts off the unnecessary flow of write current in the driver circuit, thereby eliminates power wastage in SWTHFA. Proposed SWTHFA shows improvement in power saving, output response, read and write power delay product by 38.87%, 26.45%, 40.86% and 36.53%, respectively, compared to conventional write hybrid full-adder (CWHFA). Further, we performed Monte-Carlo simulations by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ to demonstrate the feasibility of SWTHFA in low-power VLSI circuits.

Ultralow Voltage FinFET- Versus TFET-Based STT-MRAM Cells for IoT Applications

Spin-transfer torque magnetic tunnel junction (STT-MTJ) based on double-barrier magnetic tunnel junction (DMTJ) has shown promising characteristics to define low-power non-volatile memories. This, along with the combination of tunnel FET (TFET) technology, could enable the design of ultralow-power/ultralow-energy STT magnetic RAMs (STT-MRAMs) for future Internet of Things (IoT) applications. This paper presents the comparison between FinFET- and TFET-based STT-MRAM bitcells operating at ultralow voltages. Our study is performed at the bitcell level by considering a DMTJ with two reference layers and exploiting either FinFET or TFET devices as cell selectors. Although ultralow-voltage operation occurs at the expense of reduced reading voltage sensing margins, simulations results show that TFET-based solutions are more resilient to process variations and can operate at ultralow voltages (&lt;0.5 V), while showing energy savings of 50% and faster write switching of 60%.

STT-MTJ Based Smart Implication for Energy-Efficient Logic-in-Memory Computing

Spin-transfer torque magnetic tunnel junction (STT-MTJ) technology is an attractive solution for designing non-volatile Logic-in-Memory (LIM) architectures. This work explores a smart material implication (SIMPLY) LIM scheme based on nanoscale STT-MTJs. The SIMPLY architecture is benchmarked against the conventional material implication (IMPLY) logic. Obtained results prove that for similar performance the STT-MTJ based SIMPLY scheme ensures more reliable operation (i.e., lower error rate by more than three orders of magnitude) and an energy saving of −70% than its IMPLY counterpart, at the only cost of minimal area overhead.

Heavy-Ion Irradiation Effects on Advanced Perpendicular Anisotropy Spin-Transfer Torque Magnetic Tunnel Junction

This article investigates heavy-ion irradiation effects on perpendicular magnetic anisotropy spin-transfer torque magnetic tunnel junction devices (PMA STT-MTJs). The radiative campaign took place at the Université Catholique de Leuven (UCL) facility. The considered devices consist of STT p-MTJs purely magnetic memories and they were fabricated at SPINTEC using the most advanced CoFeB-MgO MTJ technology. Single-event upset (SEU) tolerance and modification of magnetic properties has been investigated.

Compact model of nanometer STT-MTJ device with scale effect

The emergence and growing maturity of spintronics present new ideas and methods for low-power integrated circuit design. Spin-transfer torque magnetic tunnel junction (STT-MTJ) device is one of the spintronic candidates for future promising non-volatile memory. In this paper, a compact model for the STT-MTJ device in nanoscale is presented. By analyzing the influence of the device scale on its properties, the scale effect of the MTJ device is included. The thermal stability factor is trimmed to reflect the error rate of the scale effect of the device. Based on the compact model, the simulation is conducted with different device sizes to present the influence of the scale effect on the device characteristics, including the resistance, the critical current, the switching time, the write error rate, and other characteristics.

Nonvolatile NULL Convention Logic Pipeline Using Magnetic Tunnel Junctions

Nowadays, energy is one of the main considerations with the increasing demands for IoTs, wearable-devices, machine learning and artificial intelligence. Asynchronous logic is a viable solution to address the energy issues owing to its advantages of no clock tree, robust circuit operation and avoidance of worst-case timing. NULL Convention Logic (NCL), one of the most popular asynchronous logic paradigms, expresses logic directly and needs minimal delay analysis. However, mainstream CMOS-based NCL still suffers from high static power issue. Spin transfer torque magnetic tunnel junction (STT-MTJ) is a potential device for low-power NCL design with the merits of non-volatility, high speed, nearly zero standby power and 3-D integration capability. In this work, we designed a novel nonvolatile NCL (NV-NCL) pipeline by integrating NCL and STT-MTJ. Compared to traditional NCL pipeline, our proposed NV-NCL pipeline exploits nonvolatile registers (NVRs) to reduce static power consumption. Meanwhile, write completion detector (WCD) was added in NVR to realize self-adaptive writing, further reducing dynamic write power. The behaviors and performance of the proposed NV-NCL pipeline were evaluated by using a 40 nm CMOS process and an in-house developed STT-MTJ model. Finally, parameter optimizations are explored to improve performance in terms of write time (∼5 ns), power consumption (∼0.48 pJ/bit) and reliability.

Hardware Security Exploiting Post-CMOS Devices: Fundamental Device Characteristics, State-of-the-Art Countermeasures, Challenges and Roadmap

Emerging nanoelectronic semiconductor devices have been quite promising in enhancing hardware-oriented security and trust. However, implementing hardware security primitives and methodologies requires large area overhead and power consumption. Furthermore, emerging new attack models and vulnerabilities are regularly evolving and cannot be adequately addressed by current CMOS technology. This paper for the first time presents a comprehensive review of numerous post-CMOS technologies based hardware security primitives and methodologies, particularly true random number generators, physically unclonable functions, sidechannel analysis countermeasures, and hardware obfuscation techniques. Various beyond-CMOS device technologies including tunneling FET (TFET), hybrid phase transition FET (HyperFET), carbon nanotube FET (CNTFET), silicon nanowire FET (SiNWFET), symmetrical tunneling FET (SymFET), phase-change memory (PCM), spin-transfer torque magnetic tunnel junction (STT-MTJ), resistive random access memory (RRAM) have been considered in this study. First, the basic principle of operation and unusual characteristics of nanoelectronic devices used for hardware security applications have been extensively discussed. Later, CMOS technology challenges and benefits of emerging nanotechnologies for the design of hardware security primitives and methodologies have been reported. Finally, different analyses have been presented to demonstrate the promising performance of post-CMOS devices over the current CMOS technology in different countermeasures. Additionally, challenges, future directions, and plans have been presented to achieve more research outcomes in this field.