Spin-transfer Torque Magnetic Random Access Research Articles

Mixed etching-oxidation process to enhance the performance of spin-transfer torque MRAM for high-performance computing

Spin-transfer torque magnetic random access memory (MRAM) devices have considerable potential for high-performance computing applications; however, progress in this field has been hindered by difficulties in etching the magnetic tunnel junction (MTJ). One notable issue is electrical shorting caused by the accumulation of etching by-products on MTJ surfaces. Attempts to resolve these issues led to the development of step-MTJs, in which etching does not proceed beyond the MgO barrier; however, the resulting devices suffer from poor scalability and unpredictable shunting paths due to asymmetric electrode structures. This paper outlines the fabrication of pillar-shaped MTJs via a four-step etching process involving reactive-ion etching, ion-beam etching, oxygen exposure, and ion-trimming. The respective steps can be cross-tuned to optimize the shape of the pillars, prevent sidewall redeposition, and remove undesired shunting paths in order to enhance MTJ performance. In experiments, the proposed pillar-MTJs outperformed step-MTJs in key metrics, including tunneling magnetoresistance, coercivity, and switching efficiency. The proposed pillar-MTJs also enable the fabrication of MRAM cells with smaller cell sizes than spin–orbit torque devices and require no external field differing from voltage-controlled magnetic anisotropy devices.

Implementing bidirectional logic with backhopping in magnetic tunnel junctions

A bidirectional logic gate has been designed based on the backhopping phenomenon observed in magnetic tunnel junctions (MTJ) at high bias. The magnetization dynamics of each magnetic layer of the MTJ—having materials and geometry of a standard spin-transfer torque magnetic random access memory device—is calculated using the coupled Landau–Lifshitz–Gilbert equation-based theoretical framework. A circuit design interconnecting the MTJs has been proposed to simulate a two-input NAND gate. The results in both forward and reverse directions agree well with those found from the Boltzmann distribution, thereby demonstrating the equiprobability of all valid states.

Effect of Edge Roughness on Resistance and Switching Voltage of Magnetic Tunnel Junctions

We investigate the impact of edge roughness on the electrical transport properties of magnetic tunnel junctions using non-equilibrium Green’s function formalism. We have modeled edge roughness as a stochastic variation in the cross-sectional profile of magnetic tunnel junction characterized by the stretched exponential decay of the correlation function. The stochastic variation in the shape and size changes the transverse energy mode profile and gives rise to variations in the resistance and switching voltage of the magnetic tunnel junction. We find that the variations are larger as the magnetic tunnel junction size is scaled down due to the quantum confinement effect. A model is proposed for the efficient calculation of edge roughness effects by approximating the cross-sectional geometry to a circle with the same cross-sectional area. Further improvement can be obtained by approximating the cross-sectional area to an ellipse with an aspect ratio determined by the first transverse eigenvalue corresponding to the 2D cross-section. These results would be useful for designing reliable spin transfer torque-magnetic random access memory (STT-MRAM) with ultra-small magnetic tunnel junctions.

Effect of MgO Grain Boundaries on the Interfacial Perpendicular Magnetic Anisotropy in Spin-Transfer Torque Magnetic Random Access Memory: A First-Principles Study

Spin-transfer torque magnetic random access memory (STT-MRAM) requires large interfacial perpendicular magnetic anisotropy (iPMA) to be maintained even after many microfabrication steps. The data retention of STT-MRAM depends on the quality of the interface between the ferromagnetic layer and the insulating layer in magnetic tunnel junction (MTJ). We have investigated the effects of the grain boundary (GB) in the MgO layer on the iPMA using first-principles calculations. The results show that the iPMA is reduced by the presence of GBs, even though some iPMA remains. This is explained by a decrease in the peak of density of states (DOS) just above the Fermi energy, and that the DOS at high energy is increased in the down spin channel for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${d}_{xz}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$d_{yz}$ </tex-math></inline-formula> orbitals. Moreover, we found that the bond structure of Fe-d orbitals around the GB is a key factor controlling the iPMA, in addition to the well-known role of interfacial Fe–O bonds.

Efficiency of Double-Barrier Magnetic Tunnel Junction-Based Digital eNVM Array for Neuro-Inspired Computing

This brief deals with the impact of spin-transfer torque magnetic random access memory (STT-MRAM) cell based on double-barrier magnetic tunnel junction (DMTJ) on the performance of a two-layer multilayer perceptron (MLP) neural network. The DMTJ-based cell is benchmarked against the conventional single-barrier MTJ (SMTJ) counterpart by means of a comprehensive evaluation carried out through a state-of-the-art device-to-algorithm simulation framework. The benchmark is based on the MNIST handwritten dataset, Verilog-A MTJ compact models developed by our group, and 0.8 V FinFET technology. Our results point out that the use of DMTJ-based STT-MRAM cells to implement digital embedded non-volatile memory (eNVM) synaptic core allows write/read energy and latency improvements of about 53%/61% and 66%/17%, respectively, as compared to the SMTJ-based equivalent design. This is achieved by ensuring a reduced area footprint and a learning accuracy of about 91%. Such results make the DMTJ-based STT-MRAM cell a good eNVM option for neuro-inspired computing.

A Low-Latency and High-Endurance MLC STT-MRAM-Based Cache System

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising cache memory candidate due to its high density, low leakage power, and nonvolatility. Multilevel cell (MLC) STT-MRAM can further increase density by storing 2 bits in one cell’s hard and soft domain, respectively. However, MLC STT-MRAM suffers two-step write, leading to high write energy, long latency, and severe lifetime degradation. Current encoding techniques propose to encode the new data to reduce the two-step data writes. However, they have two weaknesses: 1) high area overhead, e.g., recent work TSE (Hsieh et al., 2020) needs extra 37.5% MLCs and 2) prolong the write latency due to an extra read. Therefore, we propose enhanced one-step write (EOSwrite) to write data in one step. EOSwrite includes line bypassing and four intraline encoding techniques. Line bypassing schemes can bypass the writes to zero or clean lines, leading to low write/read latency. As for the intraline techniques, we propose four write modes. They utilize the data patterns and the clean data in cache lines to write data in one step, therefore reducing the data write latency. The key idea of one-step write is to write as much data as possible in the soft domain of MLC STT-MRAM. EOSwrite can greatly relieve the weaknesses of the current encoding schemes. Evaluation results show that EOSwrite can improve the lifetime of MLC STT-MRAM by 56.96%, reduce dynamic energy by 33.95%, reduce access latency by 36.95%, and improve system performance of MLC STT-MRAM by 4.30%, respectively. While the area overhead of EOSwrite is only 7.27%.

MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design

The popularity of perpendicular magnetic tunnel junction (pMTJ)-based spin-transfer torque magnetic random access memories (STT-MRAMs) is growing very fast. The performance of such memories is very sensitive to magnetic fields, including both internal and external ones. This article presents a magnetic-field-aware compact model of pMTJ, named the MFA-magnetic tunnel junction (MTJ) model, for magnetic/electrical co-simulation of MTJ/CMOS circuits. Magnetic measurement data of MTJ devices, with diameters ranging from 35 to 175 nm, are used to calibrate an in-house magnetic coupling model. This model is subsequently integrated into our developed compact pMTJ model, which is implemented in Verilog-A. The superiority of the proposed MFA-MTJ model for device/circuit co-design of STT-MRAM is demonstrated by simulating a single pMTJ as well as STT-MRAM full circuits. The design space is explored under PVT variations and various configurations of magnetic fields.

CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers

Employing a small Non-Volatile Memory (NVM) as the Persistent Journal Area (PJA) along with a DRAM-based buffer is an efficient approach to overcome DRAM vulnerability, named NVB-Buffer. Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is one of the most promising PJA candidates thanks to providing high endurance, non-volatility, and DRAM-like latency. Despite these advantages, STT-MRAM faces major reliability challenges, i.e. Retention Failure, Read Disturbance, and Write Failure, which have not been addressed in previously suggested NVB-Buffers. In this paper, we first demonstrate that the retention failure is the dominant source of errors in NVB-Buffers as it suffers from long and unpredictable page idle intervals (i.e., the time interval between two consecutive accesses to a PJA page). Then, we propose a novel NVB-Buffer management scheme, named, Cold Page Awakening (CoPA), which predictably reduces the idle time of PJA pages. To this aim, CoPA employs Distant Refreshing to periodically overwrite the vulnerable PJA page contents by opportunistically using their replica in a DRAM-based buffer. We compare CoPA with the state-of-the-art schemes over several well-known storage workloads based on physical journaling. Our evaluations show that CoPA significantly reduces the maximum page idle time, which leads to three orders of magnitude lower failure rate with negligible performance degradation (1.1%) and memory overhead (1.2%).

Design of LUT-Based LDPC Decoders for Spin-Transfer Torque Magnetic Random Access Memory

Recently, low-density parity-check (LDPC) codes have been proposed to improve the reliability of spin-transfer torque magnetic random access memory (STT-MRAM). While several research works focus on the design of LDPC codes to combat the process variation and thermal fluctuation of the STT-MRAM, we aim to tackle the high decoding latency issues by the novel design of a lookup table (LUT)-based LDPC decoder for the forward and backward (FB) processes. In this work, the channel quantizer and LUT operations of the LDPC decoder are jointly designed by minimizing the error probability estimated from the density evolution (DE) algorithm. The simulation results show that the proposed design method for a code rate of 0.9 outperforms the previous methods in terms of bit error rate (BER) performance. Furthermore, the proposed design can support the channel model of the STT-MRAM without an independent and identically distributed (i.i.d.) channel adapter.

CRP: Conditional Replacement Policy for Reliability Enhancement of STT-MRAM Caches

Driven by the trends of emerging technologies in on-chip memories, with increasing the size of last-level caches (LLCs), spin-transfer torque magnetic random access memories (STT-MRAMs) are the most promising alternative technology among the non-volatile memories (NVMs) to replace SRAMs. Despite their high density, scalability, and near-zero leakage power, the reliability of STT-MRAM LLCs is threatened by a high error rate due to their stochastic switching behavior. The error rate is highly influenced by the cache management, which necessitates redesigning the cache replacement policy based on the error behavior. In this article, we propose an error-aware cache replacement policy, namely, conditional replacement policy (CRP), to improve the reliability of STT-MRAM caches by decreasing the rate of both read disturbance and write failure. This is ascertained by nominating an appropriate data block in the cache to be replaced with an incoming data block, considering the minimum error rate. Moreover, the performance and latency of both write and read operations are considered. The simulation results show that compared with the state-of-the-art replacement policy in STT-MRAM caches, CRP reduces the total error rate by 68%. In addition, the proposed policy enhances the performance by 2% and saves energy consumption by 19%, on average. Meanwhile, the total number of writes is decreased by 41% compared with the previous scheme.

Adjusting thermal stability in double-barrier MTJ for energy improvement in cryogenic STT-MRAMs

This paper investigates the impact of thermal stability relaxation in double-barrier magnetic tunnel junctions (DMTJs) for energy-efficient spin-transfer torque magnetic random access memories (STT-MRAMs) operating at the liquid nitrogen boiling point (77 K). Our study is carried out through a macrospin-based Verilog-A compact model of DMTJ, along with a 65 nm commercial process design kit (PDK) calibrated down to 77 K under silicon measurements. Comprehensive bitcell-level electrical characterization is used to estimate the energy/latency per operation and leakage power at the memory architecture-level. As a main result of our analysis, we show that energy-efficient small-to-large embedded memories can be obtained by significantly relaxing the non-volatility requirement of DMTJ devices at room temperature (i.e., by reducing the cross-section area), while maintaining the typical 10-years retention time at cryogenic temperatures. This makes DMTJ-based STT-MRAM operating at 77 K more energy-efficient than six-transistors static random-access memory (6T-SRAM) under both read and write accesses (−56% and −37% on average, respectively). Obtained results thus prove that DMTJ-based STT-MRAM with relaxed retention time is a promising alternative for the realization of reliable and energy-efficient embedded memories operating at cryogenic temperatures.

Fabrication and Individual Addressing of STT-MRAM Bit Array With 50 nm Full Pitch

Spin-transfer torque (STT) magnetic random access memory (MRAM) is gaining commercial traction in low-density embedded and standalone memories, but the available market opportunities would grow exponentially if STT-MRAM could approach dynamic random access memory (DRAM) bit density. Of course, achieving DRAM density will require, among other things, demonstrating the ability to pattern MRAM bits at an extremely tight pitch. Here, an experimental demonstration of fabrication and electrical testing of a STT-MRAM bit array are reported. By optimizing the hard mask and ion beam etching (IBE) processes, MRAM bit arrays with a full pitch down to 50 nm are fabricated, in which the bits are individually tested using a novel bottom-point-contact method.

Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation

It is questionable whether DRAM will continue to scale and will meet the needs of next-generation systems. Therefore, significant effort is invested in research and development of novel memory technologies. One of the candidates for next-generation memory is Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM). STT-MRAM is an emerging non-volatile memory with a lot of potential that could be exploited for various requirements of different computing systems. Being a novel technology, STT-MRAM devices are already approaching DRAM in terms of capacity, frequency, and device size. Although STT-MRAM technology got significant attention of various major memory manufacturers, academic research of STT-MRAM main memory remains marginal. This is mainly due to the unavailability of publicly available detailed timing and current parameters of this novel technology, which are required to perform a reliable main memory simulation on performance and power estimation. This study demonstrates an approach to perform a cycle accurate simulation of STT-MRAM main memory, being the first to release detailed timing and current parameters of this technology from academia—essentially enabling researchers to conduct reliable system-level simulation of STT-MRAM using widely accepted existing simulation infrastructure. The results show a fairly narrow overall performance deviation in response to significant variations in key timing parameters, and the power consumption experiments identify the key power component that is mostly affected with STT-MRAM.

Proactively Invalidating Dead Blocks to Enable Fast Writes in STT-MRAM Caches

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising emerging memory technology for on-chip caches. It has a low read access time and low leakage power. Unfortunately, however, STT-MRAM suffers from its long write latency and high write energy consumption. This paper proposes a cache management technique called Proactive Invalidation (PROI) that proactively invalidates dead blocks in advance to enable fast writes in the STT-MRAM caches. Experimental evaluation shows that the proposed technique improves performance by 14&#x0025; on average compared to the baseline STT-MRAM cache. This paper also proposes two optimization techniques called Proactive Invalidation-aware Data Encoding (PIDE) and Narrowness-aware Partial Write (NPW) to minimize the energy overheads of Proactive Invalidation. Experimental results demonstrate that the total energy consumption of the STT-MRAM cache with PROI is only 1.8&#x0025; higher than the baseline when PROI is applied with PIDE and NPW.

Embedded Memories for Cryogenic Applications

The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedded memory technologies under cooling—from room temperature (300 K) down to cryogenic levels (77 K). As the temperature goes down to 77 K, six-transistor static random-access memory (6T-SRAM) presents slight improvements for static noise margin (SNM) during hold and read operations, while suffering from lower (−16%) write SNM. Gain-cell embedded DRAM (GC-eDRAM) shows significant benefits under these conditions, with read voltage margins and data retention time improved by about 2× and 900×, respectively. Non-volatile spin-transfer torque magnetic random access memory (STT-MRAM) based on single- or double-barrier magnetic tunnel junctions (MTJs) exhibit higher read voltage sensing margins (36% and 48%, respectively), at the cost of longer write access time (1.45× and 2.1×, respectively). The above characteristics make the considered memory technologies to be attractive candidates not only for high-performance computing, but also enable the possibility to bridge the gap from room-temperature to the realm of cryogenic applications that operate down to liquid helium temperatures and below.

Towards Enhanced System Efficiency while Mitigating Row Hammer

In recent years, DRAM-based main memories have become susceptible to the Row Hammer (RH) problem, which causes bits to flip in a row without accessing them directly. Frequent activation of a row, called an aggressor row , causes its adjacent rows’ ( victim ) bits to flip. The state-of-the-art solution is to refresh the victim rows explicitly to prevent bit flipping. There have been several proposals made to detect RH attacks. These include both probabilistic as well as deterministic counter-based methods. The technique of handling RH attacks, however, remains the same. In this work, we propose an efficient technique for handling the RH problem. We show that the mechanism is agnostic of the detection mechanism. Our RH handling technique omits the necessity of refreshing the victim rows. Instead, we use a small non-volatile Spin-Transfer Torque Magnetic Random Access Memory (STTRAM) that ensures no unnecessary refreshes of the victim rows on the DRAM device and thus allowing more time for normal applications in the same DRAM device. Our model relies on the migration of the aggressor rows. This accounts for removing blocking of the DRAM operations due to the refreshing of victim rows incurred in the previous solution. After extensive evaluation, we found that, compared to the conventional RH mitigation techniques, our model minimizes the blocking time of the memory that is imposed due to explicit refreshing by an average of 80.72% in the worst-case scenario and provides energy savings of about 15.82% on average, across different types of RH-based workloads. A lookup table is necessary to pinpoint the location of a particular row, which, when combined with the STTMRAM, limits the storage overhead to 0.39% of a 2 GB DRAM. Our proposed model prevents repeated refreshing of the same victim rows in different refreshing windows on the DRAM device and leads to an efficient RH handling technique.

Radiation Effects in Advanced and Emerging Nonvolatile Memories

Despite hitting major roadblocks in 2-D scaling, NAND flash continues to scale in the vertical direction and dominate the commercial nonvolatile memory market. However, several emerging nonvolatile technologies are under development by major commercial foundries or are already in small volume production, motivated by storage-class memory and embedded application drivers. These include spin-transfer torque magnetic random access memory (STT-MRAM), resistive random access memory (ReRAM), phase change random access memory (PCRAM), and conductive bridge random access memory (CBRAM). Emerging memories have improved resilience to radiation effects compared to flash, which is based on storing charge, and hence may offer an expanded selection from which radiation-tolerant system designers can choose from in the future. This review discusses the material and device physics, fabrication, operational principles, and commercial status of scaled 2-D flash, 3-D flash, and emerging memory technologies. Radiation effects relevant to each of these memories are described, including the physics of and errors caused by total ionizing dose, displacement damage, and single-event effects, with an eye toward the future role of emerging technologies in radiation environments.

Simulation Analysis of DMTJ-Based STT-MRAM Operating at Cryogenic Temperatures

This article investigates spin-transfer torque magnetic random access memories (STT-MRAMs) based on double-barrier magnetic tunnel junction (DMTJ) with two reference layers when operating at cryogenic temperatures. Our study is based on architecture-level estimations relying on preliminary bitcell-level electrical simulations, which have been carried out by exploiting a macrospin-based Verilog-A compact model of DMTJ, along with a 65 nm cryogenic-aware CMOS technology. Compared to conventional six-transistor static random access memory (6T-SRAM), DMTJ-based STT-MRAM proves to be faster under read access and less energy-hungry under both read/write accesses for medium to large memory sizes. Quantitatively, compared to its 6T-SRAM counterpart, a 2 MB DMTJ-based STT-MRAM operating at 77 K improves read access time by 28% and energy consumption by 52% and 38% for read and write operations, respectively. This is achieved while providing considerably lower leakage power (-98%) and a smaller on-chip area (by about 3×), at the only cost of worsened write access time.

Evaluating critical metals contained in spintronic memory with a particular focus on Pt substitution for improved sustainability

Thanks to their unique combination of properties: non-volatility, speed, density and write endurance, spintronic memory called spin transfer-torque Magnetic Random Access Memory (STT-MRAM) is expected to play a major role in the future development of the Internet of Things (IoT) and more generally in information and communication technologies. This type of spintronic device is usually made of materials, some of which can be classified as critical. Recent studies have evaluated critical materials contained in magnetic random access memory (Ku, 2018; European Commission, 2020 [1,2]). However, in those cases the type of memory analyzed belongs to the first generation of MRAMs developed in the early 2000s. Nowadays, the memory devices are magnetized perpendicularly to the plane of the layers and contain a synthetic antiferromagnet (SAF) that provides a high coercivity to the STT-MRAM reference layer with reduced stray field. This SAF is typically made of cobalt (Co) and platinum (Pt) multilayers antiferromagnetically coupled across a thin ruthenium (Ru) layer. Due to the high-embodied energy of platinum group metals (PGMs), a common concern when evaluating these materials is the environmental risk associated with their production. An evaluation of the environmental and economic risks of using such multilayers is first reported here, followed by a discussion of its supply risk. Substitution of Co/Pt multilayers by Co/Ni multilayers can lead to a reduction by 3–4 orders of magnitude in terms of energy requirements or global warming potential (GWP) associated with the use of these multilayers. An alternative concept based on perpendicular shape anisotropy (PSA) can also yield a reduction by 1–2 orders of magnitude in these quantities. However, for the case of STT-MRAM, tiny quantities of PGM layers are used in comparison with the mass of the silicon wafers on which these type of devices are grown. Therefore, the environmental and economic impact of the silicon wafer fabrication is found to be much higher than that of the PGM materials incorporated in the STT-MRAM stacks. Nonetheless, the high supply risk associated with PGMs remains a reason for awareness. One explored possibility is a SAF structure based on Co/Ni multilayers which can have similar performance. A second more challenging alternative is also proposed based on the aforementioned PSA concept. Finally, we address the case of several other metals identified by the European Commission as critical and used in MRAM such as W or Ta, both recently included in the EU's Conflict Minerals Regulation released in January 2021 (https://ec.europa.eu/trade/policy/in-focus/conflict-minerals-regulation/regulation-explained/, 2020 [3]).

Influence of Total Ionizing Dose on Magnetic Tunnel Junctions With Perpendicular Anisotropy

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising solution for onboard, radiation-tolerant memory for space environments. This is because magnetic tunnel junctions (MTJs) have demonstrated outstanding resilience to ionizing radiation. In this study, we examine the effect of total ionizing dose (TID) on the MTJ's thermal stability factor, intrinsic critical switching voltage, and write energy. These parameters were calculated from switching probability distribution curves taken at three different pulsewidths. Additionally, dc current hysteresis plots were obtained to measure the MTJ's tunnel magnetoresistance ratio, its dependence on voltage, and the dc current required to switch states. Tests were carried out at two TID exposure levels up to 1 Mrad(Si) on a total of 24 MTJs of varying cross section dimensions in order to identify the influence of scaling as well as to obtain statistical variation for any changes observed. Results indicate that TID exposure had small effects on the MTJ's thermal stability and critical switching voltage, which affected the write energy, especially for switching from the antiparallel (AP) to parallel (P) direction. For switching from P to AP, these changes fluctuated, suggesting that TID has multiple effects, which have competing influences on the MTJ's switching properties. The work presented here shows that, while MTJs are highly resistant to ionizing radiation, a subtle influence on some properties for the STT-MRAM write operation should be considered in radiation environment assessments for both terrestrial and space applications.