Spin-transfer Torque Magnetic Random Access Research Articles

Modeling of a Magnetic Tunnel Junction for a Multilevel STT-MRAM Cell

In the recent past, spin-transfer torque (STT) magnetic random access memories (MRAMs) have gained stupendous research interest with a potential to provide a solution for the on-chip memory applications. The prevailing single-level cell STT-MRAMs pose significant challenges due to scaling issues, making them unviable for the low-power and high-density embedded memory applications. This paper describes a pathway to design low-cost-per-bit, energy-efficient, and high-density multilevel cell (MLC) STT-MRAMs. This paper presents a model for magnetic tunnel junction (MTJ) devices based on in-plane magnetic anisotropy (IMA) and perpendicular magnetic anisotropy (PMA) using Verilog-A and elemental SPICE simulation framework. These MTJ devices are connected in series or parallel configuration to carry out a comparative performance analysis of series-MLC (sMLC) or parallel-MLC (pMLC) STT-MRAMs. The proposed model is validated using experimental results of IMA- and PMA-based sMLC and pMLC configurations, and the simulation results reveal a close agreement. The PMA-based pMLC configuration offers ultralow-voltage operation, least tunnel magnetoresistance degradations, and distinct presentation of resistance states, making it suitable for embedded memory applications.

Area and Energy Efficient Series Multilevel Cell STT-MRAMs for Optimized Read–Write Operations

With the inception of perpendicular magnetic anisotropy-based magnetic tunnel junction (PMTJ) devices, spin-transfer torque (STT) magnetic random access memory (MRAM) is considered as a promising candidate for low power high-density embedded memory applications. However, the single-level cell STT-MRAM did not create much impact due to its energy/area inefficiency, higher cost per bit, and unoptimized read/write operations in sub-50 nm regime. In this paper, a series multilevel cell (sMLC) STT-MRAM is proposed that offers higher array density with reliable and energy efficient read–write operations with minimum error rates at the lower supply voltage. A high-k dielectric metal gate-based gate-all-around vertical silicon nanowire is used to drive the sMLC. A unified model based on Verilog-A and HSPICE is employed to imitate the PMTJ device. The results of 2 bit sMLC designs demonstrate switching error probability much below $10^{-9}$ , and average write energy <2 pJ at the pulsewidth of 20 ns with a footprint area of 2F2 per bit (F is the feature size).

Energy barrier and domain wall thermal reversal in magnetic elliptic cylinders

The energy barriers are studied for an in-plane magnetized elliptic magnetoresistive random access memory cell using the nudged elastic band method with finite-element micromagnetics. Our calculations show that the transition between coherent magnetization rotation and domain wall mediated thermal reversal appears at an ellipse aspect ratio greater than 2 for widths 60-90 nm. This crossover point is almost independent of the value of the partial perpendicular magnetic anisotropy and has only a negligibly weak dependence of the width and thickness of the cell and only weakly depends on the exchange stiffness for reasonable in-plane Spin-Transfer Torque Magnetic Random Access Memory parameters. We developed an analytical model for the thermal barrier, which agrees with the numerical results.

Relation between switching time distribution and damping constant in magnetic nanostructure

It is widely known that the switching time is determined by the thermal stability parameters and external perturbations such as magnetic field and/or spin polarized current in magnetic nano-structures. Since the thermal stability parameter and switching time are crucial values in the design of spin-transfer torque magnetic random access memory, the measurement of the switching time is important in the study of the switching behavior of ferromagnetic nano-structures. In this study, we focus on the distribution of the switching time. Within the limit of a large energy barrier, a simple analytical expression between damping constant and anisotropy field with switching time distribution is obtained and confirmed by numerically solving the Fokker-Planck equation. We show that the damping constant and anisotropy field can be extracted by measuring the full width half maximum of the switching time distribution in the magnetic nano-structure devices. Furthermore, the present method can be applied to not only single nano-structure, but also inhomogeneous nano-structure arrays.

Random Number Generation by Differential Read of Stochastic Switching in Spin-Transfer Torque Memory

The true random number generator (TRNG) is a key enabling technology for cryptography and hardware authentication, which are becoming essential features in the era of the Internet of Things (IoT). Here, we present a novel TRNG concept based on the stochastic switching in spin-transfer torque magnetic random access memory (STT-MRAM). The new methodology relies on the STT-MRAM switching variations affecting the current response under applied rectangular or triangular pulses. Random numbers are extracted from the differential read of the integrated current across two stochastic switching cycles. The proposed concept passes all tests in the NIST SP-800-22 suite with no post-processing, thus supporting STT-MRAM as a promising technology for data/hardware security in the IoT.

Switching current reduction using MgO cap layer in magnetic tunnel junctions

We investigate the current induced magnetization switching properties in CoFeB/MgO/CoFeB magnetic tunnel junctions (MTJs) with the MgO cap layer. It is found that the spin-transfer-torque induced switching current density is inversely proportional to the thickness of the MgO cap layer. We attribute the origin of this behavior to the change in the effective demagnetizing field and damping factor in the free layer, which is verified by spin-torque ferromagnetic resonance measurements. Our experimental results suggest that the utilization of the MgO-cap layer in the MTJs may be useful for spintronic device designs, such as spin-transfer torque magnetic random access memories and spin torque oscillators.

Offset-Compensated High-Speed Sense Amplifier for STT-MRAMs

Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising candidate for next generation computing systems. However, with increasing process variation and decreasing supply voltage, a big design challenge of embedded STT-MRAMs is to guarantee negligible read disturbance and high yield. To deal with the read reliability challenge, an offset compensated, high-speed sense amplifier (OCHS-SA) is proposed, which is based on combining the sensing circuit and latch sense amplifier (SA). The proposed OCHS-SA scheme offers four major advantages including offset compensation, high sensing margin (SM), strong positive feedback, and latching feature with compact area. Simulation results show that the SM is at least 700 mV at VDD = 1 V with a sensing time of 3.5 ns, and it provides the lowest energy consumption/area overhead over compared SAs.

Parallel Multilevel Cell STT-MRAMs for Optimized Area Energy and Read–Write Operations

Spin-transfer torque (STT) magnetic random access memory (MRAM) is considered as a promising candidate for the next generation embedded memory applications. The advent of a perpendicular magnetic anisotropy-based magnetic tunnel junction (PMTJ) device has made the STT-MRAM viable for low-power high-density on-chip memory architectures. However, intense research efforts are still required to optimize the single-level cell and multilevel cell (MLC) STT-MRAMs in terms of area, energy, and read–write operations at ultralow power supply voltages. In this paper, a parallel MLC (pMLC) STT-MRAM (20–50 nm) is proposed to provide smaller footprint area, energy efficient, and optimized read–write operations with very low failure probabilities at the supply voltage of 1 V. These designs utilize high- ${k}$ gate dielectric gate-all-around silicon nanowire-based vertical NMOS transistor as a switching device. The PMTJ device is modeled using Verilog-A. The HSPICE simulation results affirm the suitability of pMLC designs, e.g., 3-bit pMLC design exhibits, switching error probability much less than 10−9, and average write energy of <2 pJ with minimum cell-area at the pulsewidth of 10 ns.

Effect of Geometrical Modulation on pMTJ Magnetization Reversal

Spin-transfer torque-magnetic random access memory (STT-MRAM) is one of the most prominent spintronic devices for replacing conventional electronic memory devices due to its extraordinary performance as it delivers fast operational speed, non-volatility, and a high-memory density. At advanced technology nodes, manufacturing process would invariably lead to bit on bit variation of STT-MRAM cell at wafer level. Here, we show that in a perpendicularly magnetized magnetic tunnel junction (MTJ), the in-plane demagnetizing tensor greatly influences the magnetization switching process of the free layer (FL). The geometrical asymmetricity was introduced to induce a varying in-plane demagnetizing field. This impacts the stability of the MTJ and requires a larger anisotropy to sustain an out-of-plane magnetization state. Interestingly, a faster switching of the FL comprising the MTJ is observed. This resultant rapid switching is ascribed to the nucleation of a reversal embryo at the defect.

In-Memory Processing Paradigm for Bitwise Logic Operations in STT–MRAM

In the current big data era, the memory wall issue between the processor and the memory becomes one of the most critical bottlenecks for conventional Von-Newman computer architecture. In-memory processing (IMP) or near-memory processing (NMP) paradigms have been proposed to address this problem by adding a small amount of processing units inside/near the memory. Unfortunately, although intensively studied, prior IMP/NMP platforms are practically unsuccessful because of the fabrication complexity and cost efficiency by integrating the processing units and memory on the same chip. Recently, emerging nonvolatile memories provide new possibility for efficiently implementing the IMP/NMP paradigm. In this paper, we propose a cost-efficient IMP/NMP solution in spin-transfer torque magnetic random access memory (STT–MRAM) without adding any processing units on the memory chip. The key idea behind the proposed IMP/NMP solution is to exploit the peripheral circuitry already existing inside memory (or with minimal changes) to perform bitwise logic operations. Such an IMP/NMP platform enables rather fast logic operations as the logic results can be obtained immediately through just a memory-like readout operation. Memory read and logics not, and/nand, and or/nor operations can be achieved and dynamically configured within the same STT–MRAM chip. Functionality and performance are evaluated with hybrid simulations under the 40 nm technology node.

Impact of Ta and W-based spacers in double MgO STT-MRAM free layers on perpendicular anisotropy and damping

Free layers with double MgO/CoFeB interfaces are an established solution for improving the thermal stability at small device dimensions in perpendicular spin transfer torque-magnetic random access memory devices. A thin spacer layer, composed usually of Ta, W, Hf, etc., is used to ease crystallization and improve the perpendicular magnetic anisotropy. Here, we use ferromagnetic resonance to evaluate the impact of Ta or W containing spacer layers on the intrinsic anisotropy Hk and damping α parameters. While both spacer materials enable similar tunnel magneto-resistance and anisotropy values, W typically generates a higher damping. Ta-based spacers are therefore likely better candidates for very low switching current applications.

Thermodynamic stability, magnetism and half-metallicity of various (100) surfaces of Heusler alloy Ti2FeSn

For the Ti2FeSn Heusler alloy, the thermodynamic stability, electronic and magnetic properties of the five different terminations FeFe*, TiFe, TiTi*, TiSn and SnSn* of the (100) surface have been studied by using first-principles calculations. The results show that, the TiSn termination is the most stable one while the SnSn* termination is the most unstable one. Both the density of states (DOS) and atomic magnetic moments (AMMs) of the central layers are similar to those of the bulk Ti2FeSn case due to no influence of surface effect as we expected. The TiSn and TiFe terminations exhibit half-metallic character with 100% spin-polarizations at the Fermi level and with the spin-down band gaps of 0.36eV and 0.08eV, respectively. The TiSn termination with the lowest surface energy is the most suitable one in the spin-transfer torque magnetic random access memories (STT-MRAM) devices. The spin polarizations of the FeFe*, TiTi* and SnSn* terminations are 74.9%, 72.8% and 72.1%, respectively.

Impact of spintronic memory on multicore cache hierarchy design

Spintronic memory [spin-transfer torque-magnetic random access memory (STT-MRAM)] is an attractive alternative technology to CMOS since it offers higher density and virtually no leakage current. Spintronic memory continues to require higher write energy, however, presenting a challenge to memory hierarchy design when energy consumption is a concern. This study motivates the use of STT-MRAM for the first-level caches of a multicore processor to reduce energy consumption without significantly degrading the performance. The large STT-MRAM first-level cache implementation saves leakage power. Moreover, the use of small level-0 cache regains the performance drop due to STT-MRAM long write latencies. The combination of both reduces the energy-delay product by 65% on average compared with CMOS baseline. The proposed STT hierarchy also shows good scalability over the CMOS with a few benchmarks which scale significantly better. The PARSEC and Splash2 benchmark suites are analysed running on a modern multicore platform, comparing performance, energy consumption and scalability of the spintronic cache system to a CMOS design.

Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM

Spin-transfer torque magnetic random access memory (STT-RAM) is a promising and emerging technology due to its many advantageous features such as scalability, nonvolatility, density, endurance, and fast access speed. However, the operation of STT-RAM is severely affected by environmental factors such as process variations and temperature. As the temperature rockets up in modern computing systems, it is highly desirable to understand thermal impact on STT-RAM operations and reliability. In this paper, a thermal-aware MTJ model, calibrated and validated by experimental measurements, is proposed as the basis for thoroughly thermal aware analysis of a 1T1MTJ STT-RAM cell structure. Using this model, we investigate temperature effect on memory cell access behavior in terms of access latency, energy, and reliability on a 45-nm technology node. Thermal impact on a more advanced 11-nm technology node is also evaluated in the paper. Additionally, we propose a thermal-aware design for STT-RAM sensing circuit using a body-biasing technique, which can enlarge read margin dramatically to enhance read reliability under temperature variations. Moreover, our proposed technique can suppress read disturbance effectively as well. Experimental results show that our proposed sensing circuit can enlarge read margin by 2.47 $\times$ when reading “0” and 3.15 $\times$ when reading “1,” and reduce read disturbance error rate by 55.6% on average.

Intrinsic spin dynamics in optically excited nanoscale magnetic tunnel junction arrays restored by dielectric coating

We report the all-optical observation of intrinsic spin dynamics and extraction of magnetic material parameters from arrays of sub-100 nm spin-transfer torque magnetic random access memory (STT-MRAM) devices with a CoFeB/MgO interface. To this end, the interference of surface acoustic waves with time-resolved magneto-optic signals via magneto-elastic coupling was suppressed using a dielectric coating. The efficacy of this method is demonstrated experimentally and via modeling on a nickel nanomagnet array. The magnetization dynamics for both coated nickel and STT-MRAM arrays shows a restored field-dependent Kittel mode from which the effective damping can be extracted. We observe an increased low-field damping due to extrinsic contributions from magnetic inhomogeneities and variations in the nanomagnet shape, while the intrinsic Gilbert damping remains unaffected by patterning. The data are in excellent agreement with a local resonance model and have direct implications for the design of STT-MRAM devices as well as other nanoscale spintronic technologies.

Analysis of self-heating of thermally assisted spin-transfer torque magnetic random access memory.

Thermal assistance has been shown to significantly reduce the required operation power for spin torque transfer magnetic random access memory (STT-MRAM). Proposed heating methods include modified material stack compositions that result in increased self-heating or external heat sources. In this work we analyze the self-heating process of a standard perpendicular magnetic anisotropy STT-MRAM device through numerical simulations in order to understand the relative contributions of Joule, thermoelectric Peltier and Thomson, and tunneling junction heating. A 2D rotationally symmetric numerical model is used to solve the coupled electro-thermal equations including thermoelectric effects and heat absorbed or released at the tunneling junction. We compare self-heating for different common passivation materials, positive and negative electrical current polarity, and different device thermal anchoring and boundaries resistance configurations. The variations considered are found to result in significant differences in maximum temperatures reached. Average increases of 3 K, 10 K, and 100 K for different passivation materials, positive and negative polarity, and different thermal anchoring configurations, respectively, are observed. The highest temperatures, up to 424 K, are obtained for silicon dioxide as the passivation material, positive polarity, and low thermal anchoring with thermal boundary resistance configurations. Interestingly it is also found that due to the tunneling heat, Peltier effect, device geometry, and numerous interfacial layers around the magnetic tunnel junction (MTJ), most of the heat is dissipated on the lower potential side of the magnetic junction. This asymmetry in heating, which has also been observed experimentally, is important as thermally assisted switching requires heating of the free layer specifically and this will be significantly different for the two polarity operations, set and reset.

Emerging Three-Terminal Magnetic Memory Devices

Spin-transfer torques can switch magnetizations via a current passing through a magnetic tunnel junction, an effect that is being pursued as the switching mechanism in spin-transfer torque magnetic random access memory. Three-terminal devices are also possible. One mechanism is to have a free layer that contains a domain wall that can be manipulated by spin-transfer torques and moved between two configurations that can be read by a separate connection. An alternate approach uses the recent development of spin-orbit torques, which offer an efficient way of manipulating the magnetization of a tunnel junction by current passing through an adjacent layer. These torques allow for the separation of reading and writing currents through three-terminal devices structures. This paper presents the basic principles of spin-orbit torques, the distinguishing features of spin-orbit-torque-induced magnetization dynamics as compared to magnetization dynamics driven by conventional spin-transfer torques. From the application point of view, it presents the pros and cons of spin-orbit-torque-based three-terminal devices including magnetic random access memories. Then, it discusses domain-wall-based three-terminal devices and the advantages and disadvantages of each.

Adapting &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\text{B}^{+}$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-Tree for Emerging Nonvolatile Memory-Based Main Memory

Among the emerging nonvolatile memory (NVM) technologies, some resistive memories, including phase change memory (PCM), spin-transfer torque magnetic random access memory (STT-RAM), and metal-oxide resistive RAM (ReRAM), have been considered as promising replacements of conventional dynamic RAM (DRAM) to build future main memory systems. Main memory databases can benefit from their nice features, such as their low leakage power and nonvolatility, the high density of PCM, the good read performance and low read energy consumption of STT-RAM, and the low cost of ReRAM’s crossbar architecture. However, they also have some disadvantages, such as their long write latency, high write energy, and limited lifetime, which bring challenges to database algorithm design for NVM-based memory systems. In this paper, we focus on the design of the ubiquitous $\text{B}^{+}$ -tree, aiming to make it NVM-friendly. We present a basic cost model for NVM-based memory systems which distinguishes writes from reads, and propose detailed CPU cost and memory access models for search, insert, and delete operations on a $\text{B}^{+}$ -tree. Based on the proposed models, we analyze the CPU costs and memory behaviors of the existing NVM-friendly $\text{B}^{+}$ -tree schemes, and find that they suffer from three issues. To address these issues we propose three different schemes. Experimental results show that our schemes can efficiently improve the performance, reduce the memory energy consumption, and extend the lifetime for NVM-based memory systems.

Experimental Observation of Back-Hopping With Reference Layer Flipping by High-Voltage Pulse in Perpendicular Magnetic Tunnel Junctions

Low write error rate (WER) is an important requirement for spin-transfer torque magnetic random access memory to be developed as a product. However, there have been reports about back-hopping phenomena that disturb achieving low WER. We demonstrate the experimental observation of back-hopping from the behavior of the WER in perpendicular magnetic tunnel junctions. WER decreases as pulse voltage (Vp) increases, but increases back as Vp increases further. It is attributed to the back-hopping, which originates from flipping of the reference layer (RL) and consequent alternating reversal of RL and free layer. Thus, it is necessary for the RL to be more stable and robust to avoid the back-hopping and to achieve low WER. We performed switching experiments on the devices of different stacks, which reveal back-hopping was the most severe in a magnetic tunnel junction device with the weakest coupling strength of the RL, and was significantly suppressed with a strongly coupled RL.

Influence of the Reference Layer Composition on the Back-End-of-Line Compatibility of Co/Ni-Based Perpendicular Magnetic Tunnel Junction Stacks

Spin-transfer torque magnetic random access memory (STT-MRAM) is currently explored to challenge the dynamic random access memory and embedded memory applications. Perpendicular magnetic tunnel junction (p-MTJ) stacks used in the STT-MRAM must be compatible with CMOS back-end-of-line processing, such as high perpendicular magnetic anisotropy, high tunnel magnetoresistance (TMR), and intact resistance area (RA) product at temperatures, as high as 400°C. In this paper, we deposited a bottom-pinned Co/Ni-based p-MTJ stack with a trilayered Co/spacer/CoFeB as a reference layer and a CoFeB film as the storage layer. By replacing the standard Ta spacer material with CoFeBTa, the thickness of the spacer layer can be increased from 4 to 8 Å without TMR and RA penalty, which is beneficial to process controllability. Moreover, the TMR increases for an 8 Å CoFeB polarizer from 125% to 145% for a similar RA product after a 300°C 30 min anneal. In addition, the thermal budget of the p-MTJ stack containing a CoFeBTa spacer was improved. The p-MTJ stack with a 12 Å CoFeBTa reference layer spacer can even withstand annealing at 400°C for 90 min and can retain a TMR value of 100% at RA 10 Ω · μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , while TMR dropped below 40% for the p-MTJ stack containing a pure Ta spacer layer.