Area and Energy Efficient Series Multilevel Cell STT-MRAMs for Optimized Read–Write Operations

Abstract

With the inception of perpendicular magnetic anisotropy-based magnetic tunnel junction (PMTJ) devices, spin-transfer torque (STT) magnetic random access memory (MRAM) is considered as a promising candidate for low power high-density embedded memory applications. However, the single-level cell STT-MRAM did not create much impact due to its energy/area inefficiency, higher cost per bit, and unoptimized read/write operations in sub-50 nm regime. In this paper, a series multilevel cell (sMLC) STT-MRAM is proposed that offers higher array density with reliable and energy efficient read–write operations with minimum error rates at the lower supply voltage. A high-k dielectric metal gate-based gate-all-around vertical silicon nanowire is used to drive the sMLC. A unified model based on Verilog-A and HSPICE is employed to imitate the PMTJ device. The results of 2 bit sMLC designs demonstrate switching error probability much below $10^{-9}$ , and average write energy <2 pJ at the pulsewidth of 20 ns with a footprint area of 2F2 per bit (F is the feature size).